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  • Hello all, I do not really see a problem on the GDBServer side here. a) There was some IMPORTANT information missing initially. The SIGTRAP only occurs when setting a breakpoint in CLion while the target CPU is running. This is a special case for GDB because by default GDB runs in stop mode. In this mode after a "continue" is issued, GDB becomes blocking and does not accept new commands like "R/W memory" or "Set/Clear BP". GDB keeps blocking until J-Link GDBServer respons to the continue command…

  • Hi, Currently, there is no possibility to user-extend the register description send by GDBServer to GDB at debug session start. This is also way more tricky than it sounds because some registers need to be read different from others etc. What we could do is adding a monitor command for CSR access. Would that help? We already have this for J-Link Commander: ReadCSR <RegIndex>[,<RegSize>] WriteCSR <RegIndex>,<Value>[,<RegSize>]

  • Hello, Marvell CPUs are not supported by J-Link. It may or may not work. Marvell CPUs are usually ARM-like but with small modifications from Marvell. Some of these modifications make them incompatible from the debug side. BR Alex

  • Hello, Where do you hit "Ctrl + c"? What window is active at that point? The keystrokes are send to the active window which should be the GDB client in your case, so GDBServer does not get these keystrokes. If I am getting you wrong: Can you please re-explain what exactly(!) you are doing (or post a video)? BR Alex

  • Hello, You need to distinguish between 2 builds for your flash loader: 1) Debug The debug build should have a startup etc. so that you initialize SP etc. and are able to debug your flash loader. 2) Release The release build should not rely on any startup code. The ELF / AXF file from the release build is downloaded by J-Link into RAM and then the PC is set to the different functions to execute Init() UnInit() ... J-Link will setup the SP before starting execution of the functions it has set the …

  • Hi, To clarify: If your design / MCU provides RESET and TRST they should NOT be coupled. They need to be kept separate. TRST is not needed by J-Link but if your MCU provides this pin and you do not forward it to J-Link, you need to make sure that it is pulled HIGH. If your MCU does not provide TRST, this is no problem for J-Link. If you are using SWD, you can ignore the TRST pin of your MCU completely. The TRST bridge on the SEGGER Cortex adapter is a solder option. This is because this option i…

  • Hi, This is currently not supported as it also involves switching from JTAG/FINE to the UART boot mode of the device and most customers do not have all required pins for this connected. Also, unfortunately, the connection for UART boot mode may use different pins than JTAG/FINE on some devices, which makes things even more problematic as some of the pins may not be available on the current RX adapters we offer. I have put this onto the internal ToDo list but without any schedule so far.

  • Hi, Currently, this MCU is not supported. Demand for the S6J series MCUs is relatively low but effort to add support is relatively high. If you are interested in a quote to have support for this device added as a service, please get in touch with segger.com/support/technical-support/

  • More a question for Atmel / Microchip than for SEGGER. The RTTViewer is designed to run as a stand-alone application, not as a helper that forwards its output to a 3rd party window. We cannot really help here. What is probably possible is to have a TELNET window in Atmel Studio and connect to the same port as RTTViewer usually does when selecting "existing instance". However, this again is a question for Atmel / Microchip, not SEGGER. BR Alex

  • Hello, Can you please get in touch with segger.com/ticket/ reg. this? We would need some add. information about what IDE we are talking about (link to website?), what components you would like to ship with your IDE, ... BR Alex

  • Quote from vahidajalluian: “First and foremost, is it possible to program Nand Flash via Jlink? (The NAND flash is on EMC BUS) (using related FLM (flash algorithm) and "Jlink.ini" files) ” Yes: segger.com/products/debug-prob…nand-dataflash-and-eeprom Quote from vahidajalluian: “Second, if first question answer is YES, how is it possible to do such a thing? ” See here: wiki.segger.com/Open_Flashloader Quote from vahidajalluian: “Third, How can one put a variable in external ram, should it be writ…

  • Hi, No, the cases are not sold separately. BR Alex

  • Hi, 1) You could have 6 J-Links connected to the same PC and let them flash in parallel. (By starting 6 instances of JLinkExe in parallel) 2) You could build a JTAG chain where the 6 PCBs share TDI & TDO However, 2) has the disadvantage that you need to build a chain and make sure that the lines between the PCBs do not get to long to avoid signal quality problems. Another disadvantage would be that it only works for JTAG and programming would be serialized (one PCB after another)

  • Hello, Is this a virgin device or is there already software running on it? If there is already software running on it, the SW might enter low power modes that can make the device becoming non-responsive. If there is a fallback for a device for such a case depends on the device, as it is up to the silicon vendor to provide a fallback or not. Does it work with a virgin device? BR Alex

  • What is the actual question? When you are debugging with Eclipse, you have a "resume" / "go" button. This will resume the program execution, meaning "leave debug mode and continue user program execution"

  • Hi, It works the other way around: You need to tell J-Link to what device you are connecting to (as you do for every IDE and compiler). So it is your responsibility that the settings are correct. Please note that there is no generic approach to auto-detect all devices. The max. you can detect is the CPU core incorporated in a specific device and even that has its limits. So you should make sure that your J-Links / Flashers are not swapped in your production line and suddenly are connected to dif…

  • Depends on your setup... You could also configure your Ozone project to do the following: 1) Download the BTL + app to internal flash + QSPI 2) Issue a reset to the device which halts before executing the code in internal flash 3) Set a BP onto the jump from internal flash to SDRAM 4) Let the CPU run to that point 1-4 can be automatized with Ozone projects so that your debug session would "start in SDRAM". This way there is no need to move the SDRAM init into your Ozone project etc. Alternativel…

  • Hi, Please cross out "flash breakpoints" here. This is totally unrelated. Hopefully this makes it clear: 1. J-Link is designed to work with multiple IDEs, including GDB. For most IDEs, there is no defined "Flash download start" and "flash download end" indicator. 2. In addition to 1., some IDEs download the application image section-wise / chunk wise, so immediately triggering flash download can would eventually result in the same sector being erased + programmed multiple times, which costs time…

  • Hi, The patch adapter comes with a 0.05" cable (the photos actually show the package contents). Both adapters you listed will work. However, the 9-pin Cortex-M one may be less hassle for you as nothing needs to be wired manually.