Search Results

Search results 1-20 of 1,000. There are more results available, please enhance your search parameters.

This site uses cookies. By continuing to browse this site, you are agreeing to our Cookie Policy.

  • Hi, 1) You could have 6 J-Links connected to the same PC and let them flash in parallel. (By starting 6 instances of JLinkExe in parallel) 2) You could build a JTAG chain where the 6 PCBs share TDI & TDO However, 2) has the disadvantage that you need to build a chain and make sure that the lines between the PCBs do not get to long to avoid signal quality problems. Another disadvantage would be that it only works for JTAG and programming would be serialized (one PCB after another)

  • Hello, Is this a virgin device or is there already software running on it? If there is already software running on it, the SW might enter low power modes that can make the device becoming non-responsive. If there is a fallback for a device for such a case depends on the device, as it is up to the silicon vendor to provide a fallback or not. Does it work with a virgin device? BR Alex

  • What is the actual question? When you are debugging with Eclipse, you have a "resume" / "go" button. This will resume the program execution, meaning "leave debug mode and continue user program execution"

  • Hi, It works the other way around: You need to tell J-Link to what device you are connecting to (as you do for every IDE and compiler). So it is your responsibility that the settings are correct. Please note that there is no generic approach to auto-detect all devices. The max. you can detect is the CPU core incorporated in a specific device and even that has its limits. So you should make sure that your J-Links / Flashers are not swapped in your production line and suddenly are connected to dif…

  • Depends on your setup... You could also configure your Ozone project to do the following: 1) Download the BTL + app to internal flash + QSPI 2) Issue a reset to the device which halts before executing the code in internal flash 3) Set a BP onto the jump from internal flash to SDRAM 4) Let the CPU run to that point 1-4 can be automatized with Ozone projects so that your debug session would "start in SDRAM". This way there is no need to move the SDRAM init into your Ozone project etc. Alternativel…

  • Hi, Please cross out "flash breakpoints" here. This is totally unrelated. Hopefully this makes it clear: 1. J-Link is designed to work with multiple IDEs, including GDB. For most IDEs, there is no defined "Flash download start" and "flash download end" indicator. 2. In addition to 1., some IDEs download the application image section-wise / chunk wise, so immediately triggering flash download can would eventually result in the same sector being erased + programmed multiple times, which costs time…

  • Hi, The patch adapter comes with a 0.05" cable (the photos actually show the package contents). Both adapters you listed will work. However, the 9-pin Cortex-M one may be less hassle for you as nothing needs to be wired manually.

  • Hello Giuseppe, We have located and fixed the problem. V6.60a will be released today. It will fix this problem. Once available, you can download V6.60a here: segger.com/downloads/jlink/#J-…twareAndDocumentationPack Thanks again for the report and sorry for any inconveniences caused.

  • Hello Giuseppe, Thanks for providing the log file. Is this file from start of the debug session until the end of it? It looks a bit cut off... Usually, one of the last actions should be "GDB closed connection. Shutting down..." However, here it is cut off somewhere in the middle but without any error indication etc.

  • Please note that the savebin command does not go through any flash loader routines. It simply performs a ReadMem() access from the specified address. Is your flash memory mapped readable? Or is it some kind of SPI flash etc. that is not mapped in the address space of the CPU but instead needs to be read by feeding commands etc. to an SPI controller?

  • The situation is as follows: The J-Link flash loader uses the TI lib to program the internal flash of the TMS570xxx series devices. This is because TI does not publish any information about their flash controller etc. and recommends to use the TI lib for implementing flash programming. The flash of the TMS570 series devices is ECC protected. As almost no customer wants to manually calculate the ECC for the flash image to be programmed and program that ECC as a separate file, the TI lib offers a …

  • You can use C++ line comments "// Something" withing commander scripts with no problem. Example: Source Code (5 lines)

  • Hi, Not sure what you are trying to do. Disabling a bank in flash does not change the CRC of your data file. The data file will still hold data for 3 ranges and therefore the same CRC. If you want to remove a region from the data file, you can go through the Edit -> Delete range... menu point. This will modify the ranges available in the data file and therefore also the CRC of the data file.

  • Actually, the 2 SEGGER products (J-Link EDU and SWD Isolator) are working fine together. Dozens of customers use them. It is probably the target side that is a bit problematic here. Not sure what board you use but is the board designed to also allow drawing current on the VTref pin? (pin 1) This is needed as the SWD isolator uses VTref to adjust its target buffers for the correct HIGH levels but also uses this pin to supply power to these buffers. Maybe that's the problem here: The SWD Isolator …

  • Hi, Actually, what the command is pretty self-explanatory: By default, J-Link caches the download of your application on debug session start and later uses that cached contents during trace. Reading always from target memory would be too slow for streaming trace and real-time analysis. If you need to trace without prior download or you need to trace regions that are not part of the image you have downloaded, you need to tell J-Link once to read that regions and cache them as well. This is what t…

  • We are currently working on a new multi-processing concept / solution which is expected to be completed in Q1/2020. This will then allow multiple connections via IP (if all come from the same host PC) For now, you are limited to 1 connection via IP.

  • To answer the original question: Quote from lukma: “The original question was about the possibility to emulate/generate with Segger setup the TRST and !RESET signals with micro seconds resolution. ” This is not possible right now. It may be in in a future version but not right now. For what do you need a [us] solution here?

  • Correction: It was a problem in the J-Link SW that has been fixed in recent versions (V6.48 and later). There was an internal misunderstanding. It was not a problem on the IAR EWARM side.

  • As you did not change your tools, setup, SW versions etc. there are only 2 things left: 1) You have have a bad cable etc. that has bad/unstable connection to your HW 2) You have changed your application to enter low power modes that inhibit debugger connections reg. 2) Do you have the nRESET pin of the ST device connected to J-Link, so J-Link can control it? It is mandatory to make sure that J-Link can connect to your device, no matter in what state it is. - Alex

  • FYI: No need to use the beta version (V6.23a) but the latest release will also do (V6.22e) as it has been fixed there. However, glad to hear that you are up and running. Best regards Alex