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Hello Andy, Do you have connected your four NOR flashes parallelly (1 CS, each flash occupies 8bits of the 32 data bus) or serially (only 8bit data bus is used, 1st chip is addressed through 0x000000-0x07FFFF, 2nd chip 0x080000-0x0FFFFF, etc., or different CS). Indeed you're right, the flash AT29LV040A is wrongly listed. We will change this in the next release. Regarding the "unsupported flash type / bus width" error message, we get in touch with you via PM/Email. Regards, Souhail
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Hello Pete, Hello Gerhard, I just commented any log messages out which I found are not necessary. I also set the compiler to high speed optimization and made some modification in the link file so that fits the smallest CPU with the same sector size: Atmel SAM7S32/64 (Sector size: 128 Bytes) -> 8kByte RAM Atmel SAM7S128/256/512 (Sector size: 128 Bytes) -> 32kByte RAM You find the flash loaders attached. Flash loader for SAM7S32/64 forum.segger.com/index.php/Att…251c138b26aab46f5a2f56e59 Flash loa…
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Hello Gerhard, You are right downloading to flash through the EWARM is more convenient when debugging. But the J-Link is not really the bottle-neck. The IAR flash loader is not as fast as it could be when programming the flash. The J-Link RDI flash loader is quite faster. I have done the following test: I wrote a simple application which occupies the whole flash of the SAM7S256 I used a const char array that is used in application to the fill the flash. Used components: Computer Windows 2000Pro …
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Hi Greg, There are several reasons why the CPU core can not be halted. Either the memory wait signal of the core is still enabled or CPU disables the clock (wrong PLL clock settings/CPU enters power-save mode). Therefore the core cannot communicate via JTAG. The only way to gain control of the core via JTAG is to reset it and halt it immediately. BTW: Which STR7xx are you using? Could you please do the following:- Start the J-Link commander (JLink.exe) - Set a very high JTAG-speed by typing "spe…
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Hi mtconnol, To do this, you need to do several steps:1. Modify the link file. Since we want to copy the application into internal SRAM, we must reserve some RAM for this. Therefore the DATA segments is after this area. C Source Code (127 lines) 2. Copy your embOS application into internal SRAM. We can do that in __low_level_init(). Add following lines to your __low_level_init() after PLL initialization: C Source Code (19 lines) Let me know if this solves your problem. Souhail