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  • Hi Nino thanks for your reply. As we discussed earlier in the thread and the JLINK debug file shows, the reset is not connected from the debug probe to either the FPGAs or the ARM processor. The processor is being reset by shifting a value into the DEMCR register. I looked at your manual again, I do not find a TargetReset() function defined. I only find JLINK_TIF_ActivateTargetReset() JLINK_TIF_ReleaseTargetReset() On pages 213 of the current manual (Section 7.12.2.54 and 55). Is this what you a…

  • It is awkward to reply to my own thread so many times, but I discovered that I _can_ attach to a running process and seems to mostly work. So the big hold-up really appears to be limited to the reset. I have found I can load the binary with JLINK but when I try to restart the board (running 'r' in my JLINK script) the same error occurs as in the previous instances and I need to power-cycle. So I have a lot of work arounds but still no real solution. I see that there are different reset options d…

  • Hi Nino I am attaching a jlink log file. I stared at it for a bit but was unable to be wiser based on its output, but again it fails around here on the reset. 02-00000000-00-00002141-0042: T89539700 002:148 JLINK_ResetPullsRESET(ON) (0000ms, 1298ms total) 02-00000000-00-00002195-01D3: T89539700 002:148 JLINK_Reset() -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDFC)Reset: Halt core after reset via DEMCR.VC_CORERESET.Reset: Reset device…

  • Hi Nino Yes looking at the log file I posted on the original post (well, std out of the gdb session) it looks like it fails on reset. The reset pin is not connected to the devices, so something else is going on. I will have to try to capture the J-Link log file and see what it says, if it has additional information.

  • Hi Nino Thanks for your response. I can start the command-line invocation of the gdb server command but then I don't know what to do next. It starts ok but then does not do anything if i just call it with the arguments listed above. Do you have a suggestion on what I should do to test it? The log file from previous seems to run into problems after the connect, when the system issues a reset to the processor (after line 42), and when I start gdb by hand it just waits at that point w/o doing anyth…

  • Hi, so if no one has any suggestions, can anyone give me more generic advice or experience with the combination of a JTAG chain of ARM (non-Zynq) + FPGA using SEGGER tools? Any hints or comments would be appreciated. Even an appropriate eval board I could use to ‘practice’ would be useful. Thanks Peter

  • Dear all I have a custom board that has on it a Tiva TM4C1290NCPDT MCU and two Xilinx FPGAs (Ultrascale+ devices.) These boards share a JTAG chain. Via jumpers I can select out one of the devices and program it on the test bench, but once the board is in a ATCA shelf this will not be practical and I would like to be able to program and debug the MCU while all devices are on the JTAG chain. For the debugging and loading of the TM4C firmware I have been using a SEGGER JLINK EDU in the Eclipse envi…