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  • Hello, Some production batches have boards which were previously programmed with 'allow security'. When I manually re-program these using J-Link Commander, I need to use the 'unlock kinetis' command before loading the file. How do I ensure that these can be successfully re-programmed with a stand-alone Flasher ARM? Thanks, Denis

  • Hi Nino, I think I have everything working, if I follow the exact sequence below: The connection sequence: - insert J-Link USB - Insert J-Link JTAG - Power up boardLaunch J-Link Commander The connection is important: - J-Link> connect - Device: MK81FN256XXX15 - Interface: SWD - Speed: 4000kHz It seems that in the past some of these boards were programmed with MCU "MK81FN256XXX15 enable security". - J-Link> unklock kinetis - And then load the ihex file: - J-Link> loadfile FW_and_Data.hex Thanks, …

  • I need some help troubleshooting Release: J-Link/J-Flash V6.46 or V6.48 Devices: J-Link Compact or Flasher ARM I'm trying to program NXP K81 with Internal and External flash. Using both devices, with the same .hex program file this sometimes succeeds (about 10% of the time), but mostly it fails. When using the J-Link Compact with J-Link Commander (loadfile), the internal flash load stage appears to complete successfully, but the external flash load stage sometimes fails after the compare phase: …

  • Hi Nino. Oops, that was a typo! The version I am using is V6.46 and NOT V4.46 However, I did as you suggested and downloaded V6.48. I now get : J-Link>loadfile c:\nxp\termsettings.hex InitTarget() Found SW-DP with ID 0x2BA01477 AP map detection skipped. Manually configured AP map found. AP[0]: AHB-AP (IDR: Not set) AP[0]: Core found AP[0]: AHB-AP ROM base: 0xE00FF000 CPUID register: 0x410FC241. Implementer code: 0x41 (ARM) Found Cortex-M4 r0p1, Little endian. FPUnit: 6 code (BP) slots and 2 lite…

  • I am able to load firmware with code sections on both internal flash, and external QSPI flash using, e.g., loadfile FW.hex (This functionality was available from J-Link V4.44) Now I need to load a single binary data file to an address in QSPI flash. J-Link V6.46h Try 1: J-Link>loadbin \nxp\termsettings.bin 0x68060000 Halting CPU for downloading file. Downloading file [\nxp\termsettings.bin]... Compare method "Programmed sectors, fastest method" is not supported for this device. Changed to "Progr…

  • FIXED. V6.44a Release Notes: 5. DLL: QSPI flash programming support for Freescale K80/K82 series devices, fixed.

  • I have an NXP Kinetis K81 with QSPI XiP Flash. Code sections exist on both internal and external flash. Firmware loads and runs perfectly with the J-Link under control of NXP's Eclipse-based MCUXpresso IDE. However, when the IDE is not available, and I attempt to load .hex firmware using only J-Link Commander, I get: J-Link>loadfile c:\nxp\IPS_170617-1.0-FW.hex Downloading file [c:\nxp\IPS_170617-1.0-FW.hex]... Compare method "Programmed sectors, fastest method" is not supported for this device.…

  • In the meantime I am trying to find a solution using a JLink Script, triggered from the GDB. The script runs but does not change the register as expected. C Source Code (26 lines) output: ... Verify method "Programmed sectors, fastest method" is not supported for this device. Changed to "Programmed sectors using read back" J-Link script: NXP_MK8x_QSPI.JLinkScript J-Link script: Reading QSPI->MCR: 0xFFFFFFFF <<< This is not correct - looks like the register read failed J-Link script: Writing QSPI…

  • Report Back from NXP: It appears that the QSPI endian setting is incorrectly set at 32LE (32-Bit Little-Endian) when the J-Link programs the external flash. (Follow the NXP Community thread : What is the correct QSPI Endianness for K8x?) They will be contacting Segger directly to find a solution. Kind regards, Denis

  • Hi Nino, It appears that the data is stored exactly as specified in the ihex file, and is not swapped in the toolchain. I appears that the problem occurs with direct memory-mapped reads: pairs of 32-bit words are swapped between reading from flash, and their arrival in the instruction queue. I have tried this on both my custom board (NXP MK81), and an eval board (NXP FRDM-K82F). NXP are investigating: I will let you know what they find. Kind regards, Denis

  • When programming QSPI serial flash, the word order is swapped, and execution fails (core hardfault). The device is an NXP Kinetis K8x (K81/K81 family) MCU part, with a Micron or Cypress 128Mb serial QSPI flash part. The MCU has a QSPI peripheral with XiP capability, for which the default configuration is 64-bit Little-endian. When using the external flash as a data device, the 32-bit word order is consistent and correct. However, when using the external flash for executable code, the word order …