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  • Hi Alex, As a quick update, we have finalized a build for an ARTY A7. We will proceed with our own tests next week and send you the bit file when done. Could you provide a method for sharing? Best, Mario.

  • Hi Alex, Can you please provide us with a sample constraints file for Arty with your preferred 5 JTAG pins so we can use it accordingly. Best, Mario

  • Hi Alex, Yes we are working on a FPGA build and should provide one within 2 or 3 weeks. This will not be a fully functional processor however, but will provide JTAG debugging and abstract commands interfaces to access CPU registers / CSRs and memory. We will test it by running our standard tests on it before sending it. Is that enough? We will have the bitfile generated for an ARTY board. If you need anything specific and more details please let us know.

  • Hello all, Any update on whether or not this will be implemented in the future? Best Regards, Mario.

  • Hi Alex, Thank you for your reply. The application we are using JLink for is an embedded IOT processor that is not yet in the market. System bus and Program buffer were not implemented to reduce the footprint of the SoC especially since, since you already implement abstract commands, abstract memory accesses are a relatively easy modification. I understand the frustration around the spec, but apart from checks to XLEN and some bits that need to be checked, AAM procedure is well described in sect…

  • Hello, We recently purchased a JLINK Plus compact debug probe in order to attempt and debug an RV32 processor that has no System bus access Or Program Buffer but only allows memory accesses using Abstract Commands - Access Memory (as portrayed in the Debug Spec) As such I can successfully write/read CSRs, halt and all of the basic functionality but cannot read/write memory. If we connect OpenOCD to JLINK we are able to Load a binary and access memory successfully as expected (using riscv set_mem…