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Hi Nino, I confirm you that using a jlink script file to set SetAllowSimulation to 0, the register r1 shows correctly after the 'mov' statement. But I continue to be unable to read correctly the registers r8 and the following ones. I attached a snippet of two windows (JLinkGDBSever and Eclipse) to show you exactly what I see. In the code I changed 'mov r1,lr' in 'mov r8,lr' to put into play the register r8. Let me to remember you that the error messages show up only after the cpu has changed mod…
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Hi Nino,Quote: “What faulty action are you seeing with your setup exactly? What result are you expecting and what are you getting? ” I'm again referring to the 'mov' instruction. I will try as soon as possibile your suggestion. I see the error in the JLinkGDBServer output in eclipse. So, are you able to enter secure monitor mode and stop, with a breakpoint, at "subs pc, lr, #0"? In your setup, are you able to see in the register list 'spsr_mon'? I have never seen it. Thanks for your kind support…
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Hi Nino, attached (forum.segger.com/index.php/Attachment/2180/) you find an example project that may help you to investigate the issue. At line 98 of monitor.S you find the smc call. Proceeding step by step, and after executing it, the cpu enters in secure monitor mode and jumps via monitor vectors table to sm_call entry. There you find a simple "mov r1, lr". As soon as it enters the secure monitor mode, you can observe the messages from GDBServer telling that CPU mode is invalid. Moreover, exec…
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Dear Nino, I agree with you. However, I will send you a simple asm file able to show you the problem. Let me find the time to prepare it :) . The GDBServer client is "GNU gdb (Atmel build: 487) 7.10.1.20160210-cvs". I have also tried the ARM toolchain including the client "GNU gdb (GNU Tools for ARM Embedded Processors 6-2017-q2-update) 7.12.1.20170417-git". Same results. The host and target configuration parameters are: --host=x86_64-linux-gnu --target=arm-none-eabi. The host OS is Ubuntu 16.04…
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Hi Nino, thanks for your reply. You're confusing the monitor mode debugging with the secure monitor cpu mode. It's quite a common mistake, so do not worry. The platform ATSAMA5D2x (I'm using the SAMA5D2 Xplained Ultra Evaluation Kit) uses an ARM Cortex-A5 that implements the ARM security extensions. The secure monitor mode is an ARM cpu mode that is entered in, for example, via an explicit smc call. There are other ways to enter the secure monitor mode, but we don't need to go into this. So, ple…
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Hi, I'm working on a ATSAMA5D2 platform and I have problems in debugging code that runs in secure monitor CPU mode. Stepping in the code I received the following message on JLinkGDBServer console: … ERROR: _RegNumber2RegIndex: Illegal CPU Mode Reading all registers WARNING: Register with index 74 could not be read. Reason: CPSR indicates a non-valid CPU mode. WARNING: Register with index 75 could not be read. Reason: CPSR indicates a non-valid CPU mode. WARNING: Register with index 76 could not …