Search Results

Search results 1-8 of 8.

This site uses cookies. By continuing to browse this site, you are agreeing to our Cookie Policy.

  • Hello, from previous threads in this forum, I foud out that there is a (non-public) CMSIS-RTOS1/2 layer for embOS. I also found out that Segger doesn't advise to use it because it limits the usable features. However I am in the situation that I have to provide libraries to be used in other branches of out enterprise that use other RTOSes. The required functionality in this libraries is very basic. (eg. making some accesses thread safe). Is it possible to use the CMSIS_RTOS API in the libraries (…

  • Dear Martin, thank you for the quick help. Now it works perfectly. Once again, a Segger product is woth every penny. Do you offer embOS (advanced) trainings? I understand the basics of RTOSes but at some points, I am unsure if the way I use the OS functions is really suitable/elegant. (like in the example above). Best Regards, Christian

  • Hello, I have a low priority task1 that starts an automatic ADC/DMA sequence to aquire some data in realtime. When the sequence is started, the low priority task1 suspends itsself. At the end of the sequence, a DMA complete interrupt fired and task1 is resumed and starts to process the aquired data with low priority. This works well in lower load situation, however in high CPU load situations, a higher priority task2 preempts the low priority task1 and before OS_Suspend is called, the automatic …

  • Hi Alex, thanks for the quick answer. In this case it would be nice to get some warning message instead of "successfuly secured". I think this is a bit confusing. Maybe setting Level 1 would be the thing 90+% of developers would expect to happen by calling this command since Level 2 really blocks the device and Level 1 is more or less the same as on other STM32s. Best Regards, Chris

  • Hello, I am working with a STM32K050K4, a J-Link V8.0 and software package 4.76e. When I try to secure my chip via J-Flash I get a "Chip secured successfully" message however, the chip is not secured after that. (Of course I did a Vcc reset after securing the chip). Am I doing something wrong or is the "secure chip" feature not supported on the STM32F050s? Best Regards, Chris

  • I got it fixed. My electronics guy placed an external watchdog circuit in the board and didn't tell me.

  • Hello, I am using EWARM 6.60.1 to debug an STM32F050K4 target with a J-Link V8.0. My J-Link Software is updatet to the latest version (4.76c as of today). During the start of the debug session, I am getting several "Warning: Could not set S_RESET_ST" messages in the Debug log and the LED on the J-Link is flashing in red and orange. On the first look, it appears that the start of the session was successful but debugging is unstable (I get "run out of HW breakpoints" messages with no breakpoints s…

  • Hello, I tried to use the "Enable target power" in J-Flash (enabled the checkbox in "Project settings/Production") but the power on Pin 19 of the J-Link is not enabled. (I checked with a scope). However, if I use "power on" in J-Link commander, the power on Pin 19 is enabled. Is this a bug in J-Flash or did I make a wrong assumption about the function of this checkbox. (I am using J-Link software 4.56)