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With the latest version SCR1 together with the v6.44e of the j-link software the communication works.

Hi Nino, CAREFUL. The latest update (March 2019) of their SCR1 core changed the ID to DEB11001. DEB01001 is the previous ID they used before that. Also note that the IR length changed from 4 to 5 in the latest release. See below for an excerpt of the j-link connect. Cheers Daniel Device "RISC-V" selected. Connecting to target via JTAG ConfigTargetSettings() start ConfigTargetSettings() end TotalIRLen = 5, IRPrint = 0x01 JTAG chain detection found 1 devices: #0 Id: 0xDEB11001, IRLen: 05, Unknown …

The new version of SCR1 is now online. It claims to support the debug spec version 0.13. Unfortunately the problem persists. J-link cannot connect to the SCR1 with the error message CPU-TAP not found. Connection with cheap Olimex OpenOCD works without a problem. Did ANYBODY ever tried this with j-link and gotten it to work?

Thank you for your reply. I've seen the segger wiki post regarding the SCR1. I also downloaded the SCR1/Arty SDK and tried to use it with the Segger studio. It doesn't work. What does this error message mean? ****** Error: CPU-TAP not found in JTAG chain Obviously j-link is able to communicate and identify the device. So something deeper down must be not as expected. Anyways. Syntacore apparently is working on the issue and they promised me early access to a fix. We'll see...

I've taken up this issue with Syntacore and according to them J-Link is NOT compatible with SCR1 (as of March 2019). The only supported option is to use OpenOCD.

Hi, I'm having issues connecting to a SCR1 core using a brand new J_link pod (hardware V10.1) which I specifically purchases for this task. I'm running the lastest beta J-link softwae (v6.45a) as it claims to provide support for the SCR1. I'm aware of the 1/12 SCR1 clock constraint and the jtag frequency is set to a sufficiently low clock speed (100kHz). This is the output of the connection attempt: Connecting to target via JTAG ConfigTargetSettings() start ConfigTargetSettings() end TotalIRLen …

Ok, I did some more playing around with it. J-link works fine when using JTAG frequencies > 1MHz. It doesn't like frequencies < 1MHz. With slower frequencies it can't communicate reliably, sometimes not even recognizing the CPU. (Same behaviour in J-Link commander, too). Well, at least I got something to work with now. I have to suspect that somethings' not right with my PCB. Especially I don't have any pull-up/dn installed on any of the JTAG lines. Maybe that's the problem. Unfortunately I coul…

Soooo. It turns out the problem was LPC17xx pin P2.10, which cannot be low during reset, or the boot-loader is started instead of user code. Easy to miss in the NXP documentation. HOWEVER. Now everything works fine when using a cheap $19 JTAG probe from Cooxox. However it still doesn't work when using the $300 j-link box (can't stop CPU message still there). But I'm sure it's only one of those many 100 options and switches somewhere burried in the j-link software.

I get the 'could not stop cortex-M device' message when trying to download or debug my application with Keil/J-Link/JTAG. I don't even know where to look for solving this problem. There is a possibility that the PCB design is at fault. However I wasn't able to find any information on how to correctly wire the JTAG port of my LPC1754. Do I need pull-ups/downs, what values, etc. So my questions is: 1. Is there app notes or specification or reference design on how to actually wire and connect the J…