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Happy to help Niklas. I can confirm that the board is unaltered and I have been able to program the flash by booting from SD card and then using UBoot. Unfortunately we only have two evaluation boards which are in use in different geographical locations. Thanks.

Hi Niklas, The JLink is now online. Regards

Hi Niklas, I'm happy to provide access to the board. Unfortunately I'm out of the office today but can set it up on Thursday. Regards

Hi Niklas, I've attached a JLink log from when I'm starting a debug session from Codebench. I've also attached the JFlash project in which I've added init steps. Thanks for your continued attention. Regards.

Hi Niklas, I was able to confirm that downloading to RAM and also executing from RAM both work for the target system. Output from JLink is pasted below. I understand the Zedboard has a different sized QSPI flash - could that be the reason? Also tried adding JFlash initialisation steps equivalent to the initialisation performed by the debugger under Source Codebench but still no luck. SEGGER J-Link Commander V6.18 (Compiled Aug 3 2017 16:19:59) DLL version V6.18, compiled Aug 3 2017 16:19:24 Conn…

Thanks for the advice Niklas. Cheers.

Hi Niklas, Yes that's the board I'm referring to. Any advice you can offer as to where to start? Do I need to add additional init steps to the JFlash project? Thanks.

Hi Niklas, I tried with the JFlash project you provided and I was still unable to program the flash - I've attached the zipped JLink.log for this attempt. I also tried auto-generating a new project with address size as 8KB and the resulting project file was identical to yours apart from the ID for Device0 in the JTAG section as follows:- mine Device0_ID = 0x23727093 yours Device0_ID = 0x03727093 But I think this Device is for the Programmable Logic, i.e. FPGA, within the Zynq so should not matte…

Just realised you've said "Zedboard" in your last reply. This is a different board from the ZC702 evaluation board. Any ideas whether it should work or what changes are required? "Zynq 7020" is the device type we've been instructed by Mentor to use under Sourcery Codebench so I'd assumed it would be the same under JFlash/JLink commander.

Hi Nicklas, Could you share the .jflash file you used so I can compare? I'll ask a colleague to give it a try on another ZC702 board. When running under Sourcery Codebench I've not programmed the flash just debugged my application. Thanks

Hi Niklas, Address is 0 and size is 256KB I tried reducing to 8KB but operation still failed although error messages were slightly different - see below Programming target (255 bytes, 1 range) ... - Start of determining flash info (Bank 0 @ 0xFC000000) - Error while determining flash info (Bank 0 @ 0xFC000000) - End of determining flash info - Flash bank info: - 1 * 16384 KB @ 0xFC000000 - 255 bytes could not be programmed. - Target programmed successfully - Completed after 0.083 sec Despite las…

Hi, I'm currently trying to use a J-Link Plus to program the QSPI flash on the Xilinx ZC702 board. Using JFlash I've selected Zynq 7020 as the device and can connect to the target successfully. However if I attempt to program the flash then errors are reported as follows:- Programming target (255 bytes, 1 range) ... - Start of determining flash info (Bank 0 @ 0xFC000000) - ERROR: Timeout while checking target RAM, core does not stop. (PC = 0x00000004, CPSR = 0x0000019B, LR = 0x00000014)! - ERROR…