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  • [SOLVED] JLink Addressing not Correct in RX651 Dual memory Mode

    Axumite - - J-Link/Flasher related

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    IDE: Renesas e² studio Ver 2020-10 (20.10.0). CCRX Compiler Version: 3.02.00 Target Processor: RX651 (R5F5651CDDBG) on custom board Segger Software Installed: J-Link V6.88C package Segger Tool: Jlink Ultra + Hello, I am currently developing code on the Renesas RX651 processor and I am using Jlink Ultra+ to debug my custom board. I have my RX651 configured as dual bank flash mode. When having the chip configured this way, the valid address range we get for our code flash is 0xFFE40000 – 0xFFEFFFF…