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Please mark this issue resolved. The JTAG connector pin-3 (nTRST) and pin-5 (TDI) were both grounded on the board. Cutting the traces to allow them to float appears to solve the issue with Flasher-ARM SWD programming. (Note the the grounded pins did not affect J-Link SWD programming)

I can connect with my regular J-Link Compact. However, after recent update, if I use my Flasher Arm I get: SEGGER J-Link Commander V7.70a (Compiled Aug 10 2022 16:34:16) DLL version V7.70a, compiled Aug 10 2022 16:32:56 Connecting to J-Link via USB...O.K. Firmware: J-Link / Flasher ARM V5 compiled Aug 9 2022 13:19:00 Hardware version: V5.00 J-Link uptime (since boot): 0d 00h 00m 12s S/N: XXXXXXXXX License(s): JFlash, GDB USB speed mode: High speed (480 MBit/s) IP-Addr: DHCP (no addr. received ye…

Hi, Setup: Flasher-ARM J-Flash V7.68a NXP K81(or K82) with QSPI. SWD @ 4000KHz Attempting: File->Download config & data file to Flasher Get this: Downloading file(s) to probe / programmer... - Checking if selected data fits into selected flash sectors. - Preparing DAT file range: 0x00000000 - 0x000007FF (2048 bytes). - Preparing DAT file range: 0x00000800 - 0x00000FFF (2048 bytes). -------/ CUT /-------- - Preparing DAT file range: 0x0003D000 - 0x0003D7FF (2048 bytes). - Preparing DAT file range…

Segger responded directly with the solution. Upcoming release of J-Link/J-Flash will include fix for this. Please mark as solved. Thanks.

Project Settings: SWD @ 4000kHz Target Device NXP MK81FN256xxx15 Flash Bank0 256K Internal Flash Bank1 64M External QSPI BankA Flash Bank2 Disabled Production Selected Sectors Production Erase+Program+Verify checked Production Override Timeouts erase 45000ms, program 30000ms, verify 30000ms Synopsis: With Original J-Flash V6.50a: J-Flash Production Programming F7 works Stand-alone programming works After update to J-Flash 7.60d: J-Flash Production Programming Fails - ERROR: Timeout while prepari…

Hi, Flasher ARM connected via USB to J-Flash programs NXP K8x with additional QSPI flash perfectly with Target->Production Programming (F7). The Ready/O.K. LED flashes slowly (at about 1Hz), then glows solid after about 10 secs. MCU resets and application runs. Config and Data files are downloaded to Flasher, which is then detached from PC and attached to power-supply. Now, in stand-alone mode, after pressing the PROG button, the green Ready O.K LED flashes rapidly. I allow this to continue for …

Hello, Some production batches have boards which were previously programmed with 'allow security'. When I manually re-program these using J-Link Commander, I need to use the 'unlock kinetis' command before loading the file. How do I ensure that these can be successfully re-programmed with a stand-alone Flasher ARM? Thanks, Denis

Hi Nino, I think I have everything working, if I follow the exact sequence below: The connection sequence: - insert J-Link USB - Insert J-Link JTAG - Power up boardLaunch J-Link Commander The connection is important: - J-Link> connect - Device: MK81FN256XXX15 - Interface: SWD - Speed: 4000kHz It seems that in the past some of these boards were programmed with MCU "MK81FN256XXX15 enable security". - J-Link> unklock kinetis - And then load the ihex file: - J-Link> loadfile FW_and_Data.hex Thanks, …

I need some help troubleshooting Release: J-Link/J-Flash V6.46 or V6.48 Devices: J-Link Compact or Flasher ARM I'm trying to program NXP K81 with Internal and External flash. Using both devices, with the same .hex program file this sometimes succeeds (about 10% of the time), but mostly it fails. When using the J-Link Compact with J-Link Commander (loadfile), the internal flash load stage appears to complete successfully, but the external flash load stage sometimes fails after the compare phase: …

Hi Nino. Oops, that was a typo! The version I am using is V6.46 and NOT V4.46 However, I did as you suggested and downloaded V6.48. I now get : J-Link>loadfile c:\nxp\termsettings.hex InitTarget() Found SW-DP with ID 0x2BA01477 AP map detection skipped. Manually configured AP map found. AP[0]: AHB-AP (IDR: Not set) AP[0]: Core found AP[0]: AHB-AP ROM base: 0xE00FF000 CPUID register: 0x410FC241. Implementer code: 0x41 (ARM) Found Cortex-M4 r0p1, Little endian. FPUnit: 6 code (BP) slots and 2 lite…

I am able to load firmware with code sections on both internal flash, and external QSPI flash using, e.g., loadfile FW.hex (This functionality was available from J-Link V4.44) Now I need to load a single binary data file to an address in QSPI flash. J-Link V6.46h Try 1: J-Link>loadbin \nxp\termsettings.bin 0x68060000 Halting CPU for downloading file. Downloading file [\nxp\termsettings.bin]... Compare method "Programmed sectors, fastest method" is not supported for this device. Changed to "Progr…

FIXED. V6.44a Release Notes: 5. DLL: QSPI flash programming support for Freescale K80/K82 series devices, fixed.

I have an NXP Kinetis K81 with QSPI XiP Flash. Code sections exist on both internal and external flash. Firmware loads and runs perfectly with the J-Link under control of NXP's Eclipse-based MCUXpresso IDE. However, when the IDE is not available, and I attempt to load .hex firmware using only J-Link Commander, I get: J-Link>loadfile c:\nxp\IPS_170617-1.0-FW.hex Downloading file [c:\nxp\IPS_170617-1.0-FW.hex]... Compare method "Programmed sectors, fastest method" is not supported for this device.…

In the meantime I am trying to find a solution using a JLink Script, triggered from the GDB. The script runs but does not change the register as expected. C Source Code (26 lines) output: ... Verify method "Programmed sectors, fastest method" is not supported for this device. Changed to "Programmed sectors using read back" J-Link script: NXP_MK8x_QSPI.JLinkScript J-Link script: Reading QSPI->MCR: 0xFFFFFFFF <<< This is not correct - looks like the register read failed J-Link script: Writing QSPI…

Report Back from NXP: It appears that the QSPI endian setting is incorrectly set at 32LE (32-Bit Little-Endian) when the J-Link programs the external flash. (Follow the NXP Community thread : What is the correct QSPI Endianness for K8x?) They will be contacting Segger directly to find a solution. Kind regards, Denis

Hi Nino, It appears that the data is stored exactly as specified in the ihex file, and is not swapped in the toolchain. I appears that the problem occurs with direct memory-mapped reads: pairs of 32-bit words are swapped between reading from flash, and their arrival in the instruction queue. I have tried this on both my custom board (NXP MK81), and an eval board (NXP FRDM-K82F). NXP are investigating: I will let you know what they find. Kind regards, Denis

When programming QSPI serial flash, the word order is swapped, and execution fails (core hardfault). The device is an NXP Kinetis K8x (K81/K81 family) MCU part, with a Micron or Cypress 128Mb serial QSPI flash part. The MCU has a QSPI peripheral with XiP capability, for which the default configuration is 64-bit Little-endian. When using the external flash as a data device, the 32-bit word order is consistent and correct. However, when using the external flash for executable code, the word order …