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Hello Nino, thanks for your clarification: indeed I had not yet investigated the directive .syntax unified , since everything seemed working fine (just apart from RRX) once grabbed the issue related to the inverted sequence for the fields {S} and {cond} . Anyway, good to know that using such directive permits to solve the specific issue related to RRX as well as to have a more neat correspondence with the ARM documentation: for sure I will be using it from now onward. Thanks and best regards Pao…

Hi mwb1100, Hi Nino, indeed the problem is very quickly reproduced: 1) just create a new project in ES (last version: Release 7.32 Build 2023081802.53976 ; used in non-commercial mode, as I am an academic) 2) choose "C/C++ executable for ARM/Cortex-A/R processor" (2nd choice in the menu), then 3) choose for example the TI RM57Lxxx core (I also tried the brother core TMS570LC43x, did not try others but I guess the issue will be the same at least for any core in the ARMv7 - Cortex5-R profile), 4) …

Hi mwb1100, thanks for your response. Indeed you highlighted another strange issue with the assemblers: when one sticks with the sequence of fields {S} and {cond} that is shown in the ARM manuals, which is exactly as you recalled, then one gets errors from the assembler for all of the instructions in the set, not only RRX - and this happens with both gnu and Segger toolchains! On the opposite, when you invert the sequence from {S}{cond} to {cond}{S}, then everything works fine. But, strange enou…

Hi, I am facing a strange issue with the encoding of RRX assembly instruction for a project based on TI RM57L843 Arm_v7-R microcontroller: maybe there are bugs in the assemblers? Here are simple examples of the 4 possible combinations of presence/absence of condition code and flags update for this instruction: 1 rrx r1, r0 2 rrxs r1, r0 3 rrxeq r1, r0 4 rrxeqs r1, r0 According to the documentation from ARM, all of them should be permitted by both A1 and T1 encoding, which in turn should be fully…