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After further evaluation, the memory access problems are due to the Ultrascale+ XCZU7EV7 DDR memory requiring a init procedure before it can be accessed. I'm working on creating a jlink init script using the Xilinx SDK's init process as a guide. Once I figure out the jlink equivalent init sequence I'll post a copy of the script here.

I am attempting to do a debug session on the arm R5_0 core of an Ultrascale+ XCZU7EV7 using a Jlink Plus and, so far, have had no luck getting it to work. My setup: - Xilinx ZCU104 Ulrascale+ evaluation board - SW6 is set to Jtag mode (on, on, on, on) - J-Link plus running Firmware version V10.10 - Connected to the ZCU104 via flywires to a 14pin adapter connected to J180 - Ozone debugger, or Eclipse GDB SEGGER J-Link Debugging Whenever I start a debug session I it seems to get as far as writing …