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when we select "TEST"(add via JLinkDevices.xml)，click “Target” ->"Connect J-Link",err,log as follow Connecting ‘J-Link’ using ‘USB’ Loaded C:/Program Files/SEGGER/SEGGER Embedded Studio for RISC-V 5.34/bin/JLink_x64.dll Firmware Version: J-Link V10 compiled Jan 4 2021 16:15:44 DLL Version: 6.92` Hardware Version: V10.10 Target Voltage: 3.399 Device "TEST" selected. Current Speed: 7827 kHz TotalIRLen = ?, IRPrint = 0x..000000000000000000000000 TotalIRLen = ?, IRPrint = 0x..00000000000000000000000…
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In order to add support for a new RV32 device to the J-Link DLL, new device added to the JLinkDevices.xml ,but not connect to jlink... - ERROR: The connected J-Link does not support selecting another hart/core than 0 for RISC-V Specific core setup failed. - ERROR: Failed to connect. Could not establish a connection to target. why? I want to now how to use "ConfigTargetSettings" for a universal RV32 core connect with jlink thanks.
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in the IDE：《SEGGER Embedded Studio for RISC-V x.xx 》 the TargetInterface object's member functions,why not support“ TargetInterface.runToAddress(address, timeout) ”，can you support it？ thanks
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Hi Seggers, Any update? Can this issue be reproduced?
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I have the same question. If the SVD file can be used in Embedded Studio, more old chip projects move to the IDE will be possiable. Or, Segger provide a convert tool in IDE to translate SVD file to new memory map file is another option.
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Generate a new RV32 project follow guide, or whatever project. Configure IDE use JLink-JTAG; Connect GND/VTREF to GND/VCC-3.3V like picture bellow, other pin connect nothing（just like some CPU logic fail condition）； forum.segger.com/index.php/Attachment/4531/ Then, build project and click Debug-Go button, now, the crash occur. Configuration and Demo project plz reference to attachments. By the way, this issue can be reproduced in any PC， 5 or more computers as i tested.
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Resolved by edit project file. cozd by external_build_file_name="" target to a wrong ELF file.
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Thanks for reply. V5.34 have the same issue. As i know v5.20 v5.30 has exactly the same problem. The condition is 1. Connect JLink to target(with power supply); 2. Disable CPU or Halt fail, maybe only connect JTAG VTREF Pin will works the same; 3. Configure IDE use JLink/JTAG as the debugger; 4. Use IDE to connect target or enter debug session; OS: Windows 10 Home
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IDE will crash if there's no target cpu. Is there any way configure some settings to prevent from this kind of crash. forum.segger.com/index.php/Attachment/4516/
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Address mismatch with really code in debug session. Left is Disassembly window, Right is ELF file，CPU-PC-Pointer/Really-Address-in-ELF mismatch witch in Disassembly-Window. CPU-PC-Pointer/Really-Address-in-ELF is right, but Address in Disassembly-Window is wrong. Source Code (12 lines) forum.segger.com/index.php/Attachment/4514/