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  • [SOLVED] SWD fails when Logic Analyzer is (directly) attached

    Chilippso - - J-Link/Flasher related

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    Hello together, I am having a problem tracing a SWD connection, because as soon as the clock signal line is connected to the Logic Analyzer (ADALM2000), my Segger J-Link EDU refuses to work. DUT is a custom PCB with Dialog DA14695 MCU. Schematics and PCB-Layout was done by someone else (semi-professional). There are no external pull up / down for the SWD lines since the DA14695 integrates internal ones. Their reset states are: pull-up for SWDIO and pull-down for SWCLK - according to the specs. M…