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  • [ABANDONED] J-Link and J-Flash QSPI programming issue using alternate pinouts on i.MXRT

    s.voulaz - - J-Link/Flasher related

    Post

    Hello, in our products, based on i.MXRT processors, we use alternate pinout for the QSPI flash used for boot. Although programming works generically fine, it looks like the Segger QSPI loader for these devices probes all the combination of pinouts for the primary FlexSPI controller in order to detect the correct pinout. This causes detection and/or operation problems if some pin of the primary port is used for any other function. Is there a way to instruct the QSPI loader for i.MXRT to use a spe…

  • [ABANDONED] RTT on dual core i.MXRT1176

    s.voulaz - - J-Link/Flasher related

    Post

    Hello, I am working on a project based on i.MXRT1176, where both M4 and M7 cores are used. The problem is, I can see RTT output only from application running on M7 core. Here follows some information about debug setup: - Debugging is made via two Ozone sessions (M7 in download, M4 in attach) - Each application uses its own RTT control block - Address of control blocks is correctly detected by both Ozone instances (and buffer data is ktbg) - RTT log from M7 is correctly displayed in M7 Ozone inst…