Search Results

Search results 1-11 of 11.

This site uses cookies. By continuing to browse this site, you are agreeing to our Cookie Policy.

  • Is there any update on this?

  • Hi Happy new year! We are still looking for an answer to the issue we are seeing. Can you please help us with that? Thank You!

  • Sure, thank you for the response. Looking forward to hearing back on this. Thank you!

  • Hi Alex Thank you for responding back. As per your suggestion, we did try changing JTAGConfig to 0,0 instead of -1,-1 but it didn't work for specific ManufId in IDCODE. If we remove the ManufId from IDCODE, it works without any issue. We are trying to understand why it works without ManufId but not with ManufId. Thank you!

  • Hi In reference to my previous thread Support for Ibex RV32 core we are kind of confused about the solution. We had IDCODE configured in RTL/bitstream with our specific ManufId and this was not working. As a hit-and-try method, we just made the ManufId as 0 which changed the IDCODE as 0x1 (LSB is hard-coded to 1 in IDCODE register) and it worked. We still want to use our specific ManufID and therefore want to have clarification on below queries: 1. What the J-Link commander will do with IDCODE? …

  • Hello We found the issue, it was the IDCODE which was not specified in the bitstream we were using. Once we updated it, we were able to use J-Link commander. Thank you!

  • Can anyone please reply on this? Thank you!

  • Hi I have to check whether we can provide physical access or not. But I was wondering if you can briefly explain how does J-Link reads the DMI register. I understand that for ARM it looks into ROM tables but since these tables are not applicable for RISCV, how do they read the DMI register for RISCV? Is the register address need to be memory mapped in Coresight address space or just providing the absolute address of these registers on RISCV would work? When J-Link identified the core behind the …

  • Hi Alex Yes, our setup is something like this. We are having two cores: RV32 and Cortex-M33 hooked through the JTAG chain. We did change the Core base address for RV32 but still seeing the same error. Is it possible to get an example J-Link script for this configuration? We are using below J-Link script: int InitTarget(void) { JLINK_SYS_Report("*******J-Link Script Running******"); JLINK_ExecCommand("CORESIGHT_SetCoreBaseAddr = 0xA"); JLINK_ExecCommand("CORESIGHT_SetIndexAPBAPToUse = 0x0"); retu…

  • Hi Alex Thank you for responding. We don't have any applications running yet. It's just an FPGA with Ibex core-based bitstream on it if that makes sense. We are trying to use J-Link commander for downloading the binary and running the application but this issue doesn't allow us to connect in the first place.

  • Hi We are trying to use J-Link as a Debug probe for the RISC-V-based 32-bit Ibex core, but are unable to connect it through J-Link. I am attaching a screenshot for better clarity. Can anyone please help us with that? We tried device types as RISC-V, RV32, and RV64 but got the error as per snap. Thank you.