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I can see the J-Link side is standard ARM. Target side and the adapter board is what Im trying to clarify. Ive looked in the ARM docs, thats where I found reference to the functionality but cant find anything related to those connections. So basically if you use the JTAG/SWD interface the test interface is left unconnected and debugging from startup is adversely affected - Is that the conclusion.

Regarding my first question, ARM documentation states: ARM strongly recommends that both signals areseparately available on the JTAG connector. If the nRESET and nTRSTsignals are linked together, resetting the system also resets the TAPcontroller. This means that: - It is not possible to debug a system fromreset, because any breakpoints previously set are lost. - You might have to start the debug sessionfrom the beginning, because DSTREAM might not recover when the TAPcontroller state is changed…

Hi Fabian, I've already looked at that page. 1). The line "may experience some limitations when debugging." from that page is what my first question relates to... What exactly are the limitations? Im asking so I may de-risk any issues with the interface for debugging. 2). To clarify my second question; Is the connection to pin 9, as shown in my diagram, which was drawn from the page you linked, a Segger proprietary feature? The pin is optionally connected to what seems to be, in other implementa…

I'm designing a board with a JTAG/SWD connector for use with JLink and other ICD to program and debug (not sure if SWD only will suffice). I've noticed that most Cortex M debuggers don't route the TRST through, instead using the MCU reset. Firstly, how does not being able to assert the test reset affect use of the JTAG for programming and debug? Secondly, I've noticed that the 19-Pin Cortex-M Adapter* optionally routes the test reset through to pin 9, as shown in the attached diagram. Is this st…