Search Results
Search results 1-6 of 6.
This site uses cookies. By continuing to browse this site, you are agreeing to our Cookie Policy.
-
I can confirm that "r" resets the register. Some testing notes: PLLCFGR reset value is 0x00001000 PLLCFGR address is 0x4002100C Following JLINK commander "erase", PLLCFGR value is 0x01001412 "r" resets this to 0x00001000 I've attached the jlink output log after a program attempt, which yields the wrong initial PLLCFGR value.
-
I have an issue where Segger V7.98 isn't properly resetting the device registers on startup. Example, STM32L4P5 register PLLCFGR and TAMP settings don't automatically reset to default values. I'm using Crossworks 5.0.3? on win10 if it makes any difference here. In V7.98, every time I start a debug session this PLL value is wrong. So I have to start execution, then restart before the PLLCFGR value is at the reset value. In V7.68, this happens similarly except only the first time the device is pow…
-
Is it possible to use J-link script files on the Flasher Portable PLUS or is the script PC side only?
-
I am using a STM32F769NI + micron MT25QL512 64MB memory which uses the ST_STM32F746G_Disco_QSPI.elf It works fine until I set the qspi to use 4 byte mode, after which it requires a power cycle to the board to connect. Is source available for this elf? Or is there some other workaround?
-
I am referring to the J-Link GDB Server RTOS plug-in SDK.
-
I really would like thread debug support for the cortex A processors. I recently downloaded the SDK, and see it doesn't have the Freertos code, I'd really like to know if I could get that, or perhaps someone else has worked on this already?