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Fabian, The xml from J-link dll is wrong. I have informed the chip maker Nuclei about the problem. And they will contact your company soon. Nuclei N101, according to the doc I got: QSPI flash controller address: 0x15000 QSPI flash XIP address: 0x20000-0x3FFFF RAM address: 0x80000-0x9FFFF. I think Nuclei will give you the authoritative details. BR /Li

I just found the RAM from Jlink device xml specified a wrong range for my target. After correct that, RTT viewer works fine now. It can be closed now.

J-link community, I followed wiki.segger.com/Open_Flashloader to create a customized flash loader. The SOC is nearly same as the SiFive FE310, except the RAM/Flash address are different. QSPI flash controller address: 0x15000 QSPI flash XIP address: 0x20000 Attached is my project for the flash loader. In the debug configuration, I can see the flash content are correctly loaded. But when I create the Release version and try it, I got the error: ====================== J-Link>r Reset delay: 0 ms Re…

Hello, I am trying J-Link RTT on Nuclei N101 core. Now I can successfully get the RTT message from function SEGGER_RTT_printf by "Debug Terminal" in emStudio. But if I use J-Link RTT viewer, I can't see any messages at all. The RTT viewer works well with another MCU STM32F103. Here is the output from RTT viewer log, there is nothing from the ternimal window. ================== LOG: J-Link RTT Viewer V6.80c: Logging started. LOG: Terminal 0 added. LOG: Connecting to J-Link via USB... LOG: Device …

All, I have a try with J-LINK EDU for cortex-A53 AARCH32 mode. But after the core is identified, the halt command failed. The target is on FPGA, so the coe run on 10MHz clock only. We have successfully debug the core with TRACE32 for quite a few months. So I think the core should be fine. See below logs ========================== Type "connect" to establish a target connection, '?' for help J-Link>connect Please specify device / core. <Default>: CORTEX-A53 Type '?' for selection dialog Device>? …