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Hello, when working with a RISC-V target (RV32 core with RISC-V debug interface 0.13) using J-Link Commander V6.50, I could observe the following behavior of "step" and "stepover" commands which I believe is not correct. "step" command Issuing "step" command on RISC-V target apparently does not start the processor. Instead, the instructions being stepped are simulated/interpreted within J-Link commander using cached values of registers. Only when the core is resumed (command "g"), the newly comp…

Hello, on a RISC-V (RV32) core that supports both "Program Buffer" and "System Bus Access", I can observe that J-Link Commander (V6.50) uses System Bus to access main memory (commands mem8, mem16, ... w1, w2, ...). Is there an option that would select whether JLinkExe will access the memory through one or the other approach? Having this choice is very important in practice, as ProgramBuffer will always provide hart's point of view to memory, which is on the other hand not guaranteed with System …

Hello, by observing how J-Link Commander (JLinkExe) behaves, I understand that "rreg" and "wreg" commands do not read and write to/from processor registers immediately but instead work with cached values. New values are written to the CPU registers only when the processor is resumed. Is my observation correct? An example of that situation when working with my RISC-V target: J-Link>ishalted CPU is halted. J-Link>wreg tselect 1 TSELECT = 0x00000001 J-Link>rreg 1952 TSELECT = 0x00000001 <---- TSELE…