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I made a discovery regarding this issue: The reason the jlink tools are treating the SDRAM area like flash is the fact that in the JLinkDevices.xml file in C:\Program Files (x86)\SEGGER\Jlink, the following profile is setup for the Cyclone V: <Device> <ChipInfo Vendor="Altera" Name="Cyclone V" Core="JLINK_CORE_CORTEX_A9" WorkRAMAddr="0xFFFF0000" WorkRAMSize="0x00010000" /> <FlashBankInfo Name="QSPI Flash" BaseAddr="0x00000000" MaxSize="0x02000000" Loader="Devices/Altera/Cyclone_V/Altera_Cyclone_…

Hello- I'm working with an Altera Cyclone V SoC with a Cortex A9 core. In our application, we have an external SDRAM chip mapped into memory location 0x00100000-0xC0000000 on the SoC. I have a bootloader program that is downloaded to the On-Chip RAM (0xFFFF0000-0xFFFFFFFF) on the SoC.This bootloader runs first in order to initialize the SDRAM (among other things). Once this bootloader gets to its stopping point, the SDRAM can be loaded with the application code. This sequence works great when I …