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  • LPC2132/01 FIQ interrupt handler

    MichaelE - - embOS related

    Post

    Hello. We had to add in our project LPC2132/01 FIQ interrupt handler. Due to bug in most NXP ARM based controllers, I had to disable & re enable both IRQ & FIQ bits in ARM CSPR register while refreshing CPU watchdog. Since embOS functions OS_EnableInt() / OS_DisableInt() in file OS_Priv.h only effects IRQ bit, I made my own functions which set & clear the two bits rather then only one. My question is – how can I be sure that register r12 is free, and that it is OK to do CPSR register modificat…