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Hello, I am developing the cortex-A53 based FPGA system. If I enter connect command on JLink Commander Utility, then it scans the ROM Table inside coresight SoC600. But, it stops the ROM Table scan immediately and the JLink utility prints the connection fail message (refer to the 1st attached image) When I tested it with openocd, all ROM Table entries were scanned well without connection fail. The ROM Table structure is as follows. (refer to the 2nd attached image) In my opinion, if some entries…

Thanks a lot, Alex I'll check what you said. I think the site you pointed out will be helpful.

I am designing the cortex-a35 based SoC and I have the jlink plus model (version 11). so, I am wondering if it is supported to connect cortex-a35 processor with jlink plus or other jlink models. we designed cortex-a35 based FPGA now. but, the connection to the FPGA was not successful yet with following message output. (please refer to the attached file)