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Hello Segger Embedded Studio for RISC-V helps me to debug a RISC-V processor. The debugging works great. Unfortunately, I have now run into a problem that I don't know how to solve. I have built a buffer memory that is filled by UART. As soon as this is full, an interrupt signal is generated and jumped into trap_entry. From this trap_entry follows the jump into handel_trap. The handel_trap always jumps back to itself with the command J. Unfortunately, I don't know how to change the command to ha…