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Hello, at the time being Segger JLink always selects hart #0 when it comes to RISC-V debugging. I'm trying to debug SiFive U54-MC processor that has 5 hearts and this is a very unfortunate limitation from Segger. I tried selecting the hart manually, after the link is established, by programming the needed hartsel in the dmcontrol register using the JLink scripting language, but it looks like with every operation that the debugger does (like stepping, reading/writing memory, refreshing registers,…