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  • SWD clock signal Rise and Fall time out of specification with J-link plus

    shyamal.vyas - - J-Link/Flasher related

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    We have been using Segger J-Link plus for debug and programming purpose of one of our project development having RA6T1 Renesas MCU series. While testing JTAG SWD signal programming, we are capturing clock signals having rise and fall time in range of ~7ns. Whereas as per the JTAG SWD specification in Renesas RA6T1 MCU datasheet, the maximum rise and fall time limitation is 5ns: [img]https://ci3.googleusercontent.com/meips/ADKq_NZ8lcoPkMLrINTzJV9bCr1H1JTgVWmKGa39K2-L8_PwxjnvdVoebYQilrVPJk4XLgzgrx…