Hello all, I am using Version V3.03.01 uCos_III within a LPC2925 ARM9 processor. The debugging pod is a J-link base version 9.2. I used the sample code for uCos_III from your website. I have added the code to the build. - I check within RAM memory and found "SEGGER RTT" string marking the being of the RTT control block at a memory location of 0x8000222c. SystemView should be able to find the control block, but doesn't Sometimes I get " Bad JTAG communications write to IR: Expected 0x1, got 0x0 T…