int ConfigTargetSettings(void) {
    JLINK_CORESIGHT_AddAP(0, CORESIGHT_APB_AP); // Cortex_R52
	JLINK_CORESIGHT_AddAP(1, CORESIGHT_AHB_AP);
	JLINK_CORESIGHT_AddAP(2, CORESIGHT_AHB_AP); // Cortex_M7_0 (The main core)
	JLINK_CORESIGHT_AddAP(3, CORESIGHT_AHB_AP); // Cortex_M7_1
	JLINK_CORESIGHT_AddAP(4, CORESIGHT_AHB_AP);
    JLINK_CORESIGHT_IndexAPBAPToUse = 0;
	JLINK_CORESIGHT_CoreBaseAddr = 0xe00b0000;
	JLINK_CPU = 0x1404FFFF; // https://forum.segger.com/index.php/Thread/9256-Wrong-CPU-type-for-CORTEX-R52-in-the-jlink-script/
	JLINK_ExecCommand("CORESIGHT_SetCSCTICoreBaseAddr=0xe00c0000");
	
   return 0;
}
/*********************************************************************
*
*       InitTarget
*/
void InitTarget(void) {
 
  int v;
  int Ctrl;
  
  Report("******************************************************");
  Report("J-Link script for C030_R52");
  Report("******************************************************");
  
  JTAG_AllowTAPReset = 0; // J-Link is allowed to use a TAP reset for JTAG-chain auto-detection

  //
  // Power-up complete DAP
  //
  v = 0
       | (1 << 30)    // System power-up
       | (1 << 28)    // Debug popwer-up
	   | (1 << 5)     // Clear STICKYERR
       ;
  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_CTRL_STAT, 0, v);
  
  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_SELECT, 0, (2 << 24) | (0 << 4));  // Select AP[2], bank 0
  Ctrl =  0
       | (2 << 0)    // AP-access size. Fixed to 2: 32-bit
       | (1 << 4)    // Auto increment TAR after read/write access. 
	                 // After a successful Data Read/Write Register access, the address in the TAR is incremented by the size of the access.
       | (1 << 31)   // Enable software access to the Debug APB bus.
       ;
  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_CTRL, 1, Ctrl);
  
  //v = JLINK_CORESIGHT_ReadDP(JLINK_CORESIGHT_DP_REG_SELECT);
  //JLINK_SYS_Report1("JLINK_CORESIGHT_DP_REG_SELECT data: ", v);
  
  Report("===> Write 0x12345678 -> addr 0x30000000");
  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_ADDR, 0x30000000);
  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_DATA, 0x12345678);
  
  Report("===> Release Cortex_R52");
  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_ADDR, 0x40001018);
  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_DATA, 0xC3C300A5);
}