/*********************************************************************
 *
 *       ConfigTargetSettings
 */
int ConfigTargetSettings(void) {
	JLINK_ExecCommand("SetCFIFlash 0x60000000-0x60FFFFFF");    // Defaults: NumChips = 1, NumBits = 16
	// JLINK_ExecCommand("SetCFIFlash 0x64000000-0x64FFFFFF, 1, 16"); // Identical to the above
	JLINK_ExecCommand("SetWorkRAM 0x20000000-0x2000FFFF");
	return 0;
}

// int HandleBeforeFlashProg(void) {
int SetupTarget(void) {
	int r;

	r = 0;

    JLINK_SYS_Report("Configure NOR FLASH");
	JLINK_TARGET_Halt();
	JLINK_ExecCommand("SetCFIFlash 0x60000000-0x60FFFFFF");    // Defaults: NumChips = 1, NumBits = 16
	// JLINK_ExecCommand("SetCFIFlash 0x64000000-0x64FFFFFF, 1, 16"); // Identical to the above
	JLINK_ExecCommand("SetWorkRAM 0x20000000-0x2000FFFF");
	// r |= JLINK_MEM_WriteU32(0x40021014, 0x00000114);    // RCC_AHBENR, FSMC clock enable
	// r |= JLINK_MEM_WriteU32(0x40021018, 0x000001FD);    // GPIOD~G clock enable
	// r |= JLINK_MEM_WriteU32(0x40011400, 0xB4BB44BB);    // GPIOD low config, NOE, NWE => Output, NWAIT => Input
	// r |= JLINK_MEM_WriteU32(0x40011404, 0xBBBBBBBB);    // GPIOD high config, A16-A18
	// r |= JLINK_MEM_WriteU32(0x40011800, 0xBBBBBBBB);    // GPIOE low config, A19-A23
	// r |= JLINK_MEM_WriteU32(0x40011804, 0xBBBBBBBB);    // GPIOE high config, D5-D12
	// r |= JLINK_MEM_WriteU32(0x40011C00, 0x44BBBBBB);    // GPIOF low config, A0-A5
	// r |= JLINK_MEM_WriteU32(0x40011C04, 0xBBBB4444);    // GPIOF high config, A6-A9
	// r |= JLINK_MEM_WriteU32(0x40012000, 0x44BBBBBB);    // GPIOG low config, A10-A15
	// r |= JLINK_MEM_WriteU32(0x40012004, 0x444B4BB4);    // GPIOG high config, NE2 => output
	// r |= JLINK_MEM_WriteU32(0xA0000008, 0x00001059);    // CS control reg 2, 16-bit, write enable, Type: NOR flash
	// r |= JLINK_MEM_WriteU32(0xA000000C, 0x10000505);    // CS2 timing reg (read access)
	// r |= JLINK_MEM_WriteU32(0xA000010C, 0x10000505);    // CS2 timing reg (write access)

    // Delay(200);
    // TODO:
    // Disable watchdog
    // Set flash wait states
    // Set PLL / RCC
    // Delay
    // Set PLL and Devider
    // Delay
    // select amster clock

    // Enable FMC AHB Clock
    r |= JLINK_MEM_WriteU32(0x580244D4, 0x1000);
    r |= JLINK_MEM_WriteU32(0x58024534, 0x1000);

    // Enable Clock of GPIOD-I
    r |= JLINK_MEM_WriteU32(0x580244E0, 0x7F8);

    // Delay(200);

    // Set GPIOs to alternate function for FMC

    // GPIOD
    r |= JLINK_MEM_WriteU32(0x58020C0C, 0x15555500);
    r |= JLINK_MEM_WriteU32(0x58020C00, 0xAAAAAAFF);
    r |= JLINK_MEM_WriteU32(0x58020C04, 0x0);
    r |= JLINK_MEM_WriteU32(0x58020C08, 0xFFFFF00);
    r |= JLINK_MEM_WriteU32(0x58020C20, 0xCCCCCCCC);
    r |= JLINK_MEM_WriteU32(0x58020C24, 0xCCCCCCCC);
    r |= JLINK_MEM_WriteU32(0x58020C14, 0x0);

    // GPIOE
    r |= JLINK_MEM_WriteU32(0x5802100C, 0x55555555);
    r |= JLINK_MEM_WriteU32(0x58021000, 0xAAAAAAAA);
    r |= JLINK_MEM_WriteU32(0x58021004, 0x0);
    r |= JLINK_MEM_WriteU32(0x58021008, 0xFFFFFFFF);
    r |= JLINK_MEM_WriteU32(0x58021020, 0xCCCCCCCC);
    r |= JLINK_MEM_WriteU32(0x58021024, 0xCCCCCCCC);
    r |= JLINK_MEM_WriteU32(0x58021014, 0x0);

    // GPIOF
    r |= JLINK_MEM_WriteU32(0x5802140C, 0x55555555);
    r |= JLINK_MEM_WriteU32(0x58021400, 0xAAAAAAAA);
    r |= JLINK_MEM_WriteU32(0x58021404, 0x0);
    r |= JLINK_MEM_WriteU32(0x58021408, 0xFFFFFFFF);
    r |= JLINK_MEM_WriteU32(0x58021420, 0xCCCCCCCC);
    r |= JLINK_MEM_WriteU32(0x58021424, 0xCCCCCCCC);
    r |= JLINK_MEM_WriteU32(0x58021414, 0x0);

    // GPIOG
    r |= JLINK_MEM_WriteU32(0x5802180C, 0x55555555);
    r |= JLINK_MEM_WriteU32(0x58021800, 0xAAAAAAAA);
    r |= JLINK_MEM_WriteU32(0x58021804, 0x0);
    r |= JLINK_MEM_WriteU32(0x58021808, 0xFFFFFFFF);
    r |= JLINK_MEM_WriteU32(0x58021820, 0xCCCCCCCC);
    r |= JLINK_MEM_WriteU32(0x58021824, 0xCCCCCCCC);
    r |= JLINK_MEM_WriteU32(0x58021814, 0x0);

    // GPIOH
    r |= JLINK_MEM_WriteU32(0x58021C0C, 0x55555555);
    r |= JLINK_MEM_WriteU32(0x58021C00, 0xAAAAAAAA);
    r |= JLINK_MEM_WriteU32(0x58021C04, 0x0);
    r |= JLINK_MEM_WriteU32(0x58021C08, 0xFFFFFFFF);
    r |= JLINK_MEM_WriteU32(0x58021C20, 0xCCCCCCCC);
    r |= JLINK_MEM_WriteU32(0x58021C24, 0xCCCCCCCC);
    r |= JLINK_MEM_WriteU32(0x58021C14, 0x0);

    // GPIOI
    r |= JLINK_MEM_WriteU32(0x5802200C, 0x55555555);
    r |= JLINK_MEM_WriteU32(0x58022000, 0xAAAAAAAA);
    r |= JLINK_MEM_WriteU32(0x58022004, 0x0);
    r |= JLINK_MEM_WriteU32(0x58022008, 0xFFFFFFFF);
    r |= JLINK_MEM_WriteU32(0x58022020, 0xCCCCCCCC);
    r |= JLINK_MEM_WriteU32(0x58022024, 0xCCCCCCCC);
    r |= JLINK_MEM_WriteU32(0x58022014, 0x0);

    // GPIOJ
    r |= JLINK_MEM_WriteU32(0x5802240C, 0x55555555);
    r |= JLINK_MEM_WriteU32(0x58022400, 0xAAAAAAAA);
    r |= JLINK_MEM_WriteU32(0x58022404, 0x0);
    r |= JLINK_MEM_WriteU32(0x58022408, 0xFFFFFFFF);
    r |= JLINK_MEM_WriteU32(0x58022420, 0xCCCCCCCC);
    r |= JLINK_MEM_WriteU32(0x58022424, 0xCCCCCCCC);
    r |= JLINK_MEM_WriteU32(0x58022414, 0x0);

    // GPIOK
    r |= JLINK_MEM_WriteU32(0x5802280C, 0x55555555);
    r |= JLINK_MEM_WriteU32(0x58022800, 0xAAAAAAAA);
    r |= JLINK_MEM_WriteU32(0x58022804, 0x0);
    r |= JLINK_MEM_WriteU32(0x58022808, 0xFFFFFFFF);
    r |= JLINK_MEM_WriteU32(0x58022820, 0xCCCCCCCC);
    r |= JLINK_MEM_WriteU32(0x58022824, 0xCCCCCCCC);
    r |= JLINK_MEM_WriteU32(0x58022814, 0x0);

    // FMC (Just copied from svd dump)
    r |= JLINK_MEM_WriteU32(0x52004000, 0x8010B0D9); // BCR1
    r |= JLINK_MEM_WriteU32(0x52004004, 0x10340519); // BTR1
    r |= JLINK_MEM_WriteU32(0x52004008, 0x000030D2); // BCR2
    r |= JLINK_MEM_WriteU32(0x5200400C, 0x0FFFFFFF); // BTR2
    r |= JLINK_MEM_WriteU32(0x52004010, 0x000030D2); // BCR3
    r |= JLINK_MEM_WriteU32(0x52004014, 0x0FFFFFFF); // BTR3
    r |= JLINK_MEM_WriteU32(0x52004018, 0x000030D2); // BCR4
    r |= JLINK_MEM_WriteU32(0x5200401C, 0x0FFFFFFF); // BTR4
    r |= JLINK_MEM_WriteU32(0x52004080, 0x00000018); // PCR
    r |= JLINK_MEM_WriteU32(0x52004088, 0xFCFCFCFC); // PMEM  // NAND FLASH TIMING
    r |= JLINK_MEM_WriteU32(0x5200408C, 0xFCFCFCFC); // PATT  // NAND FLASH TIMING
    r |= JLINK_MEM_WriteU32(0x52004104, 0x0FFFFFFF); // BWTR1  // REST VALUE
    r |= JLINK_MEM_WriteU32(0x5200410C, 0x0FFFFFFF); // BWTR2  // REST VALUE
    r |= JLINK_MEM_WriteU32(0x52004114, 0x0FFFFFFF); // BWTR3  // REST VALUE
    r |= JLINK_MEM_WriteU32(0x5200411C, 0x0FFFFFFF); // BWTR4  // REST VALUE
    r |= JLINK_MEM_WriteU32(0x52004140, 0x00001AD0); // SDCR1  // CONTROL / TIMING SDRAM
    r |= JLINK_MEM_WriteU32(0x52004144, 0x000001E5); // SDCR2  // CONTROL / TIMING SDRAM
    r |= JLINK_MEM_WriteU32(0x52004148, 0x0F1F6FFF); // SDTR1  // CONTROL / TIMING SDRAM
    r |= JLINK_MEM_WriteU32(0x5200414C, 0x01010361); // SDTR2  // CONTROL / TIMING SDRAM
    r |= JLINK_MEM_WriteU32(0x52004150, 0x00046000); // SDCMR  // SDRAM COMMAND MEMORY REGISTER
    r |= JLINK_MEM_WriteU32(0x52004154, 0x00001844); // SDRTR  // SDRAM REFRESH RATE

    // r |= JLINK_MEM_WriteU32(SDSR, 0x00000000);
    // r |= JLINK_MEM_WriteU32(SR, 0x00000040);
    // r |= JLINK_MEM_WriteU32(ECCR, 0x00000000);

	if (r < 0) {
		return -1;
	}
	return 0;
}

int HandleAfterFlashProg(void) {
	JLINK_TARGET_Halt();
    return 0;
}