Wed Sep 14, 2022 10:28:35: IAR Embedded Workbench 9.10.1 (C:\Program Files\ICCARM9\arm\bin\armPROC.dll) 
Wed Sep 14, 2022 10:28:35: Loaded macro file: C:\Program Files\ICCARM9\arm\config\debugger\NXP\iMXRT.dmac 
Wed Sep 14, 2022 10:28:35: Loaded macro file: C:\Program Files\ICCARM9\arm\config\debugger\NXP\iMXRT_Trace.dmac 
Wed Sep 14, 2022 10:28:35: None of the application was placed in flash memory. 
Wed Sep 14, 2022 10:28:35: Downloaded "path"\hello_world_SEGGER.out to flash memory. 
Wed Sep 14, 2022 10:28:35: 0 bytes downloaded into FLASH (0.00 Kbytes/sec) 
Wed Sep 14, 2022 10:28:35: Loaded macro file: "path"\hello_world_SEGGER/evkbimxrt1050/evkbimxrt1050_sdram_init.mac 
Wed Sep 14, 2022 10:28:35: JLINK command: ProjectFile = "path"\hello_world_SEGGER\settings\hello_world_SEGGER_sdram_txt_debug.jlink, return = 0 
Wed Sep 14, 2022 10:28:35: Device "MIMXRT1052XXXXB" selected. 
Wed Sep 14, 2022 10:28:35: DLL version: V7.52d, compiled Aug 17 2021 17:15:01 
Wed Sep 14, 2022 10:28:35: Firmware: J-Link V9 compiled May  7 2021 16:26:12 
Wed Sep 14, 2022 10:28:35: Selecting SWD as current target interface. 
Wed Sep 14, 2022 10:28:35: JTAG speed is initially set to: 32 kHz 
Wed Sep 14, 2022 10:28:35: Found SW-DP with ID 0x0BD11477 
Wed Sep 14, 2022 10:28:35: DPIDR: 0x0BD11477 
Wed Sep 14, 2022 10:28:35: Scanning AP map to find all available APs 
Wed Sep 14, 2022 10:28:35: AP[1]: Stopped AP scan as end of AP map has been reached 
Wed Sep 14, 2022 10:28:35: AP[0]: AHB-AP (IDR: 0x04770041) 
Wed Sep 14, 2022 10:28:35: Iterating through AP map to find AHB-AP to use 
Wed Sep 14, 2022 10:28:35: AP[0]: Core found 
Wed Sep 14, 2022 10:28:35: AP[0]: AHB-AP ROM base: 0xE00FD000 
Wed Sep 14, 2022 10:28:35: CPUID register: 0x411FC271. Implementer code: 0x41 (ARM) 
Wed Sep 14, 2022 10:28:35: Found Cortex-M7 r1p1, Little endian. 
Wed Sep 14, 2022 10:28:35: FPUnit: 8 code (BP) slots and 0 literal slots 
Wed Sep 14, 2022 10:28:35: CoreSight components: 
Wed Sep 14, 2022 10:28:35: ROMTbl[0] @ E00FD000 
Wed Sep 14, 2022 10:28:35: ROMTbl[0][0]: E00FE000, CID: B105100D, PID: 000BB4C8 ROM Table 
Wed Sep 14, 2022 10:28:35: ROMTbl[1] @ E00FE000 
Wed Sep 14, 2022 10:28:35: ROMTbl[1][0]: E00FF000, CID: B105100D, PID: 000BB4C7 ROM Table 
Wed Sep 14, 2022 10:28:35: ROMTbl[2] @ E00FF000 
Wed Sep 14, 2022 10:28:35: ROMTbl[2][0]: E000E000, CID: B105E00D, PID: 000BB00C SCS-M7 
Wed Sep 14, 2022 10:28:35: ROMTbl[2][1]: E0001000, CID: B105E00D, PID: 000BB002 DWT 
Wed Sep 14, 2022 10:28:35: ROMTbl[2][2]: E0002000, CID: B105E00D, PID: 000BB00E FPB-M7 
Wed Sep 14, 2022 10:28:35: ROMTbl[2][3]: E0000000, CID: B105E00D, PID: 000BB001 ITM 
Wed Sep 14, 2022 10:28:35: ROMTbl[1][1]: E0041000, CID: B105900D, PID: 001BB975 ETM-M7 
Wed Sep 14, 2022 10:28:36: ROMTbl[1][2]: E0042000, CID: B105900D, PID: 004BB906 CTI 
Wed Sep 14, 2022 10:28:36: ROMTbl[0][1]: E0040000, CID: B105900D, PID: 000BB9A9 TPIU-M7 
Wed Sep 14, 2022 10:28:36: ROMTbl[0][2]: E0043000, CID: B105F00D, PID: 001BB101 TSG 
Wed Sep 14, 2022 10:28:36: Cache: Separate I- and D-cache. 
Wed Sep 14, 2022 10:28:36: I-Cache L1: 32 KiB, 512 Sets, 32 Bytes/Line, 2-Way 
Wed Sep 14, 2022 10:28:36: D-Cache L1: 32 KiB, 256 Sets, 32 Bytes/Line, 4-Way 
Wed Sep 14, 2022 10:28:36: ResetTarget() start 
Wed Sep 14, 2022 10:28:36: Core did not halt on reset vector. Assuming faulty image. 
Wed Sep 14, 2022 10:28:36: Resetting and halting core on image verification value read. 
Wed Sep 14, 2022 10:28:36: Core did not halt after reset step 1 
Wed Sep 14, 2022 10:28:36: ResetTarget() end 
Wed Sep 14, 2022 10:28:37: Hardware reset with strategy 0 was performed 
Wed Sep 14, 2022 10:28:37: Initial reset was performed 
Wed Sep 14, 2022 10:28:38: FlexRAM configuration is restored 
Wed Sep 14, 2022 10:28:38: DCDC trim value loaded. 
Wed Sep 14, 2022 10:28:38: clock init done 
Wed Sep 14, 2022 10:28:39: SDRAM init done 
Wed Sep 14, 2022 10:28:39: execUserPreload() done. 
Wed Sep 14, 2022 10:28:39: Loaded debugee: "path"\hello_world_SEGGER\sdram_txt_debug\hello_world_SEGGER.out 
Wed Sep 14, 2022 10:28:39: 10996 bytes downloaded and verified (67.54 Kbytes/sec) 
Wed Sep 14, 2022 10:28:39: Download completed and verification successful. 
Wed Sep 14, 2022 10:28:39: ResetTarget() start 
Wed Sep 14, 2022 10:28:40: Core did not halt on reset vector. Assuming faulty image. 
Wed Sep 14, 2022 10:28:40: Resetting and halting core on image verification value read. 
Wed Sep 14, 2022 10:28:40: Core did not halt after reset step 1 
Wed Sep 14, 2022 10:28:40: ResetTarget() end 
Wed Sep 14, 2022 10:28:40: Software reset was performed 
Wed Sep 14, 2022 10:28:40: Failed to read SP and PC from vector table at 0x8000'0000 
Wed Sep 14, 2022 10:28:40: Target reset 
Wed Sep 14, 2022 10:28:40: FlexRAM configuration is restored 
Wed Sep 14, 2022 10:28:40: DCDC trim value loaded. 
Wed Sep 14, 2022 10:28:40: clock init done 
Wed Sep 14, 2022 10:28:40: SDRAM init done 
Wed Sep 14, 2022 10:28:40: execUserReset() done. 
Wed Sep 14, 2022 10:28:40: There was 1 warning during the initialization of the debugging session.