/* Master related */ #define EXAMPLE_LPSPI_MASTER_BASEADDR (LPSPI1) #define EXAMPLE_LPSPI_MASTER_DMA_MUX_BASE (DMAMUX1) #define EXAMPLE_LPSPI_MASTER_DMA_RX_REQUEST_SOURCE kDmaRequestMuxLPSPI1Rx #define EXAMPLE_LPSPI_MASTER_DMA_TX_REQUEST_SOURCE kDmaRequestMuxLPSPI1Tx #define EXAMPLE_LPSPI_MASTER_DMA_BASE (DMA1) #define EXAMPLE_LPSPI_MASTER_DMA_RX_CHANNEL 0U #define EXAMPLE_LPSPI_MASTER_DMA_TX_CHANNEL 1U #define EXAMPLE_LPSPI_MASTER_PCS_FOR_INIT (kLPSPI_Pcs0) #define EXAMPLE_LPSPI_MASTER_PCS_FOR_TRANSFER (kLPSPI_MasterPcs0) #define LPSPI_MASTER_CLK_FREQ (CLOCK_GetFreqFromObs(CCM_OBS_LPSPI1_CLK_ROOT)) #define EXAMPLE_LPSPI_DEALY_COUNT 0xFFFFFU #define TRANSFER_BAUDRATE 8000000U //500000U /* Transfer baudrate - 500k */ void LPSPI_MasterUserCallback(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, status_t status, void *userData); AT_NONCACHEABLE_SECTION_INIT(uint8_t masterRxData1[TRANSFER_SIZE]) = {0}; AT_NONCACHEABLE_SECTION_INIT(uint8_t masterTxData1[TRANSFER_SIZE]) = {0}; AT_NONCACHEABLE_SECTION_INIT(lpspi_master_edma_handle_t g_m_edma_handle) = {0}; edma_handle_t lpspiEdmaMasterRxRegToRxDataHandle; edma_handle_t lpspiEdmaMasterTxDataToTxRegHandle; volatile bool isTransferCompleted = false; void dmaspi_example( void ) { uint32_t srcClock_Hz; uint32_t errorCount; uint32_t loopCount = 1U; uint32_t i; lpspi_master_config_t masterConfig; lpspi_transfer_t masterXfer; edma_config_t userConfig; //BOARD_ConfigMPU(); /* done before in an other function */ //BOARD_InitPins(); done in lines after : CLOCK_EnableClock(kCLOCK_Iomuxc); /* LPCG on: LPCG is ON. */ IOMUXC_SetPinMux( IOMUXC_GPIO_AD_28_LPSPI1_SCK, 0U ); IOMUXC_SetPinMux( IOMUXC_GPIO_AD_29_LPSPI1_PCS0, 0U ); IOMUXC_SetPinMux( IOMUXC_GPIO_AD_30_LPSPI1_SOUT, 0U ); IOMUXC_SetPinMux( IOMUXC_GPIO_AD_31_LPSPI1_SIN, 0U ); IOMUXC_SetPinConfig( IOMUXC_GPIO_AD_28_LPSPI1_SCK, 0x02U ); IOMUXC_SetPinConfig( IOMUXC_GPIO_AD_29_LPSPI1_PCS0, 0x02U ); IOMUXC_SetPinConfig( IOMUXC_GPIO_AD_30_LPSPI1_SOUT, 0x02U ); IOMUXC_SetPinConfig( IOMUXC_GPIO_AD_31_LPSPI1_SIN, 0x02U ); //BOARD_BootClockRUN(); done before, in an other function //BOARD_InitDebugConsole(); /*DMA Mux setting and EDMA init*/ #if defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT /* DMA MUX init*/ DMAMUX_Init(EXAMPLE_LPSPI_MASTER_DMA_MUX_BASE); DMAMUX_SetSource(EXAMPLE_LPSPI_MASTER_DMA_MUX_BASE, EXAMPLE_LPSPI_MASTER_DMA_RX_CHANNEL, EXAMPLE_LPSPI_MASTER_DMA_RX_REQUEST_SOURCE); DMAMUX_EnableChannel(EXAMPLE_LPSPI_MASTER_DMA_MUX_BASE, EXAMPLE_LPSPI_MASTER_DMA_RX_CHANNEL); DMAMUX_SetSource(EXAMPLE_LPSPI_MASTER_DMA_MUX_BASE, EXAMPLE_LPSPI_MASTER_DMA_TX_CHANNEL, EXAMPLE_LPSPI_MASTER_DMA_TX_REQUEST_SOURCE); DMAMUX_EnableChannel(EXAMPLE_LPSPI_MASTER_DMA_MUX_BASE, EXAMPLE_LPSPI_MASTER_DMA_TX_CHANNEL); #endif /* EDMA init*/ /* * userConfig.enableRoundRobinArbitration = false; * userConfig.enableHaltOnError = true; * userConfig.enableContinuousLinkMode = false; * userConfig.enableDebugMode = false; */ EDMA_GetDefaultConfig(&userConfig); EDMA_Init(EXAMPLE_LPSPI_MASTER_DMA_BASE, &userConfig); /*Master config*/ LPSPI_MasterGetDefaultConfig(&masterConfig); masterConfig.baudRate = TRANSFER_BAUDRATE; masterConfig.whichPcs = EXAMPLE_LPSPI_MASTER_PCS_FOR_INIT; srcClock_Hz = LPSPI_MASTER_CLK_FREQ; LPSPI_MasterInit(EXAMPLE_LPSPI_MASTER_BASEADDR, &masterConfig, srcClock_Hz); /*Set up lpspi master*/ memset(&(lpspiEdmaMasterRxRegToRxDataHandle), 0, sizeof(lpspiEdmaMasterRxRegToRxDataHandle)); memset(&(lpspiEdmaMasterTxDataToTxRegHandle), 0, sizeof(lpspiEdmaMasterTxDataToTxRegHandle)); EDMA_CreateHandle(&(lpspiEdmaMasterRxRegToRxDataHandle), EXAMPLE_LPSPI_MASTER_DMA_BASE, EXAMPLE_LPSPI_MASTER_DMA_RX_CHANNEL); EDMA_CreateHandle(&(lpspiEdmaMasterTxDataToTxRegHandle), EXAMPLE_LPSPI_MASTER_DMA_BASE, EXAMPLE_LPSPI_MASTER_DMA_TX_CHANNEL); LPSPI_MasterTransferCreateHandleEDMA(EXAMPLE_LPSPI_MASTER_BASEADDR, &g_m_edma_handle, LPSPI_MasterUserCallback, NULL, &lpspiEdmaMasterRxRegToRxDataHandle, &lpspiEdmaMasterTxDataToTxRegHandle); while (1) { /* Set up the transfer data */ for (i = 0U; i < TRANSFER_SIZE; i++) { masterTxData[i] = (i + loopCount) % 256U; masterRxData[i] = 0U; } /*Start master transfer*/ masterXfer.txData = masterTxData; masterXfer.rxData = NULL; masterXfer.dataSize = TRANSFER_SIZE; masterXfer.configFlags = EXAMPLE_LPSPI_MASTER_PCS_FOR_TRANSFER | kLPSPI_MasterByteSwap | kLPSPI_MasterPcsContinuous; isTransferCompleted = false; prio = NVIC_GetPriority(DMA0_DMA16_IRQn ); prio = NVIC_GetPriority(DMA1_DMA17_IRQn ); LPSPI_MasterTransferEDMA(EXAMPLE_LPSPI_MASTER_BASEADDR, &g_m_edma_handle, &masterXfer); /* Wait until transfer completed */ while (!isTransferCompleted) { } /* Start master transfer, receive data from slave */ isTransferCompleted = false; masterXfer.txData = NULL; masterXfer.rxData = masterRxData; masterXfer.dataSize = TRANSFER_SIZE; masterXfer.configFlags = EXAMPLE_LPSPI_MASTER_PCS_FOR_TRANSFER | kLPSPI_MasterByteSwap | kLPSPI_MasterPcsContinuous; LPSPI_MasterTransferEDMA(EXAMPLE_LPSPI_MASTER_BASEADDR, &g_m_edma_handle, &masterXfer); /* Wait until transfer completed */ while (!isTransferCompleted) { } errorCount = 0; for (i = 0; i < TRANSFER_SIZE; i++) { if (masterTxData[i] != masterRxData[i]) { errorCount++; } } if (errorCount == 0) { } else { } loopCount++; } }