Logging started @ 2019-02-05 09:54
DLL Compiled: Jul 14 2017 17:23:19

Firmware: J-Link ARM Lite V8 compiled Mar 14 2018 16:03:26
Hardware: V8.00
S/N: 228201027
Feature(s): GDB
TELNET listener socket opened on port 19021WEBSRV 
Webserver running on local port 19080  returns O.K. (0009ms, 0010ms total)
T1034 000:010 JLINK_ExecCommand("ProjectFile = C:\Users\niaar\Project\Template\IAR\settings\project_Debug.jlink", ...).   returns 0x00 (0090ms, 0100ms total)
T1034 000:100 JLINK_ExecCommand("device = cortex m3 based (edited)", ...). Device "cortex m3 based (edited)" selected.  returns 0x00 (0003ms, 0103ms total)
T1034 000:103 JLINK_GetDLLVersion()  returns 61608 (0000ms, 0103ms total)
T1034 000:103 JLINK_GetCompileDateTime() (0000ms, 0103ms total)
T1034 000:104 JLINK_GetFirmwareString(...) (0000ms, 0104ms total)
T1034 000:104 JLINK_TIF_Select(JLINKARM_TIF_SWD)  returns 0x00 (0000ms, 0104ms total)
T1034 000:104 JLINK_SelectDeviceFamily(3) (0000ms, 0104ms total)
T1034 000:104 JLINK_SetSpeed(1000) (0000ms, 0104ms total)
T1034 000:104 JLINK_ExecCommand("SetResetType = 0", ...).   returns 0x01 (0000ms, 0104ms total)
T1034 000:104 JLINK_ExecCommand("SetResetPulseLen = 200", ...).   returns 0x14 (0000ms, 0104ms total)
T1034 000:104 JLINK_SetResetDelay(0) (0000ms, 0104ms total)
T1034 000:104 JLINK_ResetPullsRESET(ON) (0000ms, 0104ms total)
T1034 000:104 JLINK_Reset() >0x10B TIF>Found SW-DP with ID 0x2BA01477 >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF>Scanning APs, stopping at first AHB-AP found. >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF>AP[0] IDR: 0x24770011 (AHB-AP) >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF>AHB-AP ROM: 0xE00FF000 (Base addr. of first ROM table) >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF>
 >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF>CPUID reg: 0x412FC230. Implementer code: 0x41 (ARM)Found Cortex-M3 r2p0, Little endian. -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE0002000)FPUnit: 6 code (BP) slots and 2 literal slots -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000)
 -- CPU_WriteMem(4 bytes @ 0xE0001000) -- CPU_ReadMem(4 bytes @ 0xE000ED88) -- CPU_WriteMem(4 bytes @ 0xE000ED88) -- CPU_ReadMem(4 bytes @ 0xE000ED88) -- CPU_WriteMem(4 bytes @ 0xE000ED88)CoreSight components:ROMTbl[0] @ E00FF000 -- CPU_ReadMem(16 bytes @ 0xE00FF000) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) -- CPU_ReadMem(16 bytes @ 0xE000EFE0)ROMTbl[0][0]: E000E000, CID: B105E00D, PID: 002BB000 SCS -- CPU_ReadMem(16 bytes @ 0xE0001FF0) -- CPU_ReadMem(16 bytes @ 0xE0001FE0)
ROMTbl[0][1]: E0001000, CID: B105E00D, PID: 002BB002 DWT -- CPU_ReadMem(16 bytes @ 0xE0002FF0) -- CPU_ReadMem(16 bytes @ 0xE0002FE0)ROMTbl[0][2]: E0002000, CID: B105E00D, PID: 002BB003 FPB -- CPU_ReadMem(16 bytes @ 0xE0000FF0) -- CPU_ReadMem(16 bytes @ 0xE0000FE0)ROMTbl[0][3]: E0000000, CID: B105E00D, PID: 002BB001 ITM -- CPU_ReadMem(16 bytes @ 0xE00FF010) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) -- CPU_ReadMem(16 bytes @ 0xE0040FE0)ROMTbl[0][4]: E0040000, CID: B105900D, PID: 002BB923 TPIU-Lite
 -- CPU_ReadMem(16 bytes @ 0xE0041FF0) -- CPU_ReadMem(16 bytes @ 0xE0041FE0)ROMTbl[0][5]: E0041000, CID: B105900D, PID: 002BB924 ETM-M3 -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDFC)Reset: Halt core after reset via DEMCR.VC_CORERESET. >0x35 TIF>Reset: Reset device via AIRCR.VECTRESET. -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
 -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(32768 bytes @ 0x20000000) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC)Reset: Halt core after reset via DEMCR.VC_CORERESET. >0x35 TIF>Reset: Reset device via AIRCR.VECTRESET. -- CPU_WriteMem(4 bytes @ 0xE000ED0C)
 -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Reset: VECTRESET has confused core.Reset: Failed. Toggling reset pin and trying reset strategy again. >0x10B TIF> >0x10F TIF> >0x10B TIF> >0x10F TIF> >0x0D TIF> >0x0D TIF> >0x0D TIF>
  ***** Error: DAP error while reading DP-Ctrl-Stat register.Reset: Halt core after reset via DEMCR.VC_CORERESET. >0x35 TIF>Reset: Reset device via AIRCR.VECTRESET.Reset: CPU may have not been reset (DHCSR.S_RESET_ST never gets set). -- CPU_ReadMem(4 bytes @ 0xE000EDFC)
 -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0001000) (1350ms, 1454ms total)

Closed