SEGGER J-Link Commander V6.16h (Compiled Jul 14 2017 17:23:54)
DLL version V6.16h, compiled Jul 14 2017 17:23:19

Connecting to J-Link via USB...O.K.
Firmware: J-Link ARM Lite V8 compiled Mar 14 2018 16:03:26
Hardware version: V8.00
S/N: 228201027
License(s): GDB
VTref = 3.351V


Type "connect" to establish a target connection, '?' for help
J-Link>connect
Please specify device / core. <Default>: cortex m3 based (edited)
Type '?' for selection dialog
Device>
Please specify target interface:
  J) JTAG (Default)
  S) SWD
TIF>S
Specify target interface speed [kHz]. <Default>: 4000 kHz
Speed>
Device "cortex m3 based (edited)" selected.


Connecting to target via SWD
Found SW-DP with ID 0x2BA01477
Scanning APs, stopping at first AHB-AP found.
AP[0] IDR: 0x24770011 (AHB-AP)
AHB-AP ROM: 0xE00FF000 (Base addr. of first ROM table)
CPUID reg: 0x412FC230. Implementer code: 0x41 (ARM)
Found Cortex-M3 r2p0, Little endian.
FPUnit: 6 code (BP) slots and 2 literal slots
CoreSight components:
ROMTbl[0] @ E00FF000
ROMTbl[0][0]: E000E000, CID: B105E00D, PID: 002BB000 SCS
ROMTbl[0][1]: E0001000, CID: B105E00D, PID: 002BB002 DWT
ROMTbl[0][2]: E0002000, CID: B105E00D, PID: 002BB003 FPB
ROMTbl[0][3]: E0000000, CID: B105E00D, PID: 002BB001 ITM
ROMTbl[0][4]: E0040000, CID: B105900D, PID: 002BB923 TPIU-Lite
ROMTbl[0][5]: E0041000, CID: B105900D, PID: 002BB924 ETM-M3
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via AIRCR.VECTRESET.
Cortex-M3 identified.
J-Link>mem32 0
Syntax: mem32 <Addr>, <NumItems>
J-Link>mem32 0,4
Could not read memory.
J-Link>mem32 0,4
Could not read memory.
J-Link>r
Reset delay: 0 ms
Reset type NORMAL: Resets core & peripherals via SYSRESETREQ & VECTRESET bit.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via AIRCR.VECTRESET.
Reset: VECTRESET has confused core.
Reset: Failed. Toggling reset pin and trying reset strategy again.
Found SW-DP with ID 0x2BA01477
SWD speed too high. Reduced from 2000 kHz to 1350 kHz for stability
Using pre-configured AP[0] as AHB-AP to communicate with core
AHB-AP ROM: 0xE00FF000 (Base addr. of first ROM table)
CPUID reg: 0x412FC230. Implementer code: 0x41 (ARM)
Found Cortex-M3 r2p0, Little endian.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via AIRCR.VECTRESET.
J-Link>r
Reset delay: 0 ms
Reset type NORMAL: Resets core & peripherals via SYSRESETREQ & VECTRESET bit.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via AIRCR.VECTRESET.
J-Link>h
PC = 00001624, CycleCnt = 00000000
R0 = 00000000, R1 = 00000000, R2 = 00000000, R3 = 00000000
R4 = 00000000, R5 = 00000000, R6 = 00000000, R7 = 00000000
R8 = 00000000, R9 = 00000000, R10= 00000000, R11= 00000000
R12= 00000000
SP(R13)= 20000490, MSP= 20000490, PSP= 00000000, R14(LR) = FFFFFFFF
XPSR = 01000000: APSR = nzcvq, EPSR = 01000000, IPSR = 000 (NoException)
CFBP = 00000000, CONTROL = 00, FAULTMASK = 00, BASEPRI = 00, PRIMASK = 00
J-Link>erase
Erasing device (cortex m3 based (edited))...

****** Error: Failed to download RAMCode.
Failed to prepare for programming.
Failed to download RAMCode!
ERROR: Erase returned with error code -1.
J-Link>