Wed Sep 20, 2017 15:45:19: Loaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.2\arm\config\debugger\ST\STM32F7xx.dmac 
Wed Sep 20, 2017 15:45:19: Loaded macro file: C:\Lavori\AB90ASxx\PROG\AB90B\save_trace_buffer.mac 
Wed Sep 20, 2017 15:45:19: JLINK command: ProjectFile = C:\Lavori\AB90ASxx\PROG\AB90B\EWARM\settings\AB90B_AB90B.jlink, return = 0 
Wed Sep 20, 2017 15:45:19: Device "STM32F746BG" selected. 
Wed Sep 20, 2017 15:45:19: DLL version: V6.20a, compiled Sep 15 2017 18:04:38 
Wed Sep 20, 2017 15:45:19: Firmware: J-Link V9 compiled Sep 15 2017 17:51:55 
Wed Sep 20, 2017 15:45:19: JTAG speed is initially set to: 32 kHz 
Wed Sep 20, 2017 15:45:19: TotalIRLen = 9, IRPrint = 0x0011 
Wed Sep 20, 2017 15:45:19: JTAG chain detection found 2 devices: 
Wed Sep 20, 2017 15:45:19:  #0 Id: 0x5BA00477, IRLen: 04, CoreSight JTAG-DP 
Wed Sep 20, 2017 15:45:19:  #1 Id: 0x06449041, IRLen: 05, Unknown device 
Wed Sep 20, 2017 15:45:21: Device was not unsecured. No action performed. 
Wed Sep 20, 2017 15:45:31: Device was not unsecured. No action performed. 
Wed Sep 20, 2017 15:45:31: TotalIRLen = 9, IRPrint = 0x0011 
Wed Sep 20, 2017 15:45:31: JTAG chain detection found 2 devices: 
Wed Sep 20, 2017 15:45:31:  #0 Id: 0x5BA00477, IRLen: 04, CoreSight JTAG-DP 
Wed Sep 20, 2017 15:45:31:  #1 Id: 0x06449041, IRLen: 05, Unknown device 
Wed Sep 20, 2017 15:45:31: Scanning AP map to find all available APs 
Wed Sep 20, 2017 15:45:32: AP[0]: Stopped AP scan as end of AP map seems to be reached 
Wed Sep 20, 2017 15:45:32: Iterating through AP map to find AHB-AP to use 
Wed Sep 20, 2017 15:45:32: Scanning AP map to find all available APs 
Wed Sep 20, 2017 15:45:32: AP[1]: Stopped AP scan as end of AP map has been reached 
Wed Sep 20, 2017 15:45:32: AP[0]: AHB-AP (IDR: 0x74770001) 
Wed Sep 20, 2017 15:45:32: Iterating through AP map to find AHB-AP to use 
Wed Sep 20, 2017 15:45:32: AP[0]: Core found 
Wed Sep 20, 2017 15:45:32: AP[0]: AHB-AP ROM base: 0xE00FD000 
Wed Sep 20, 2017 15:45:32: CPUID register: 0x410FC271. Implementer code: 0x41 (ARM) 
Wed Sep 20, 2017 15:45:32: Found Cortex-M7 r0p1, Big endian. 
Wed Sep 20, 2017 15:45:32: FPUnit: 8 code (BP) slots and 0 literal slots 
Wed Sep 20, 2017 15:45:32: CoreSight components: 
Wed Sep 20, 2017 15:45:32: ROMTbl[0] @ E00FD000 
Wed Sep 20, 2017 15:45:32: ROMTbl[0][0]: E00FE000, CID: B105100D, PID: 000BB4C8 ROM Table 
Wed Sep 20, 2017 15:45:32: ROMTbl[1] @ E00FE000 
Wed Sep 20, 2017 15:45:32: ROMTbl[1][0]: E00FF000, CID: B105100D, PID: 000BB4C7 ROM Table 
Wed Sep 20, 2017 15:45:32: ROMTbl[2] @ E00FF000 
Wed Sep 20, 2017 15:45:32: ROMTbl[2][0]: E000E000, CID: B105E00D, PID: 000BB00C SCS 
Wed Sep 20, 2017 15:45:32: ROMTbl[2][1]: E0001000, CID: B105E00D, PID: 000BB002 DWT 
Wed Sep 20, 2017 15:45:32: ROMTbl[2][2]: E0002000, CID: B105E00D, PID: 000BB00E FPB 
Wed Sep 20, 2017 15:45:33: ROMTbl[2][3]: E0000000, CID: B105E00D, PID: 000BB001 ITM 
Wed Sep 20, 2017 15:45:33: ROMTbl[1][1]: E0041000, CID: B105900D, PID: 000BB975 ETM-M7 
Wed Sep 20, 2017 15:45:33: ROMTbl[0][1]: E0040000, CID: B105900D, PID: 000BB9A9 TPIU-M7 
Wed Sep 20, 2017 15:45:33: Cache: Separate I- and D-cache. 
Wed Sep 20, 2017 15:45:33: I-Cache L1: 4 KB, 64 Sets, 32 Bytes/Line, 2-Way 
Wed Sep 20, 2017 15:45:33: D-Cache L1: 4 KB, 32 Sets, 32 Bytes/Line, 4-Way 
Wed Sep 20, 2017 15:45:33: Reset: Halt core after reset via DEMCR.VC_CORERESET. 
Wed Sep 20, 2017 15:45:33: Reset: Reset device via AIRCR.SYSRESETREQ. 
Wed Sep 20, 2017 15:45:33: Hardware reset with strategy 0 was performed 
Wed Sep 20, 2017 15:45:33: Initial reset was performed 
Wed Sep 20, 2017 15:45:33: Found 2 JTAG devices, Total IRLen = 9: 
Wed Sep 20, 2017 15:45:33:  #0 Id: 0x5BA00477, IRLen:  4, IRPrint: 0x1 CoreSight JTAG-DP 
Wed Sep 20, 2017 15:45:33:  #1 Id: 0x06449041, IRLen:  5, Unknown device 
Wed Sep 20, 2017 15:46:05: Fatal error: No matching RAMCode found Failed to prepare for programming. Failed to download RAMCode!   Session aborted! 
Wed Sep 20, 2017 15:46:05: Failed to load debugee: C:\Lavori\AB90ASxx\PROG\AB90B\EWARM\AB90B\Exe\AB90B.out