/* @postcondition: target CPU to be halted / in debug mode */
void ResetTarget(void) {
  Report("BCM2836 Cortex-A7_0 ResetTarget");
}


void SetupTarget(void) {
  U32 v;

  Report("***************************************************");
  Report("BCM2836 Cortex-A7_0 SetupTarget");
  Report("***************************************************");

  //JLINK_MEM_WriteU32(0x80000FB0, 0); // DBG_LOCKACCESS
  v = JLINK_MEM_ReadU32(0x80000088); // DBG_DSCR
  v |= (7 << 13); // MDBGen, HDBGen, ITen
  JLINK_MEM_WriteU32(0x80000088, v);
}

/*********************************************************************
* InitTarget: do not auto-find, but hard code here
*/
void InitTarget(void) {
  U32 v;
  Report("***************************************************");
  Report("BCM2836 Cortex-A7_0 InitTarget");
  Report("***************************************************");
  CPU = CORTEX_A7;  // Pre-select that we have a Cortex-A7 connected

  // ARMv7A TRM D1.4.1 PADDRDBG defines this address for external debug address
  // Pointer to ROM table is somewhere within this 4 KB block
  CORESIGHT_CoreBaseAddr = 0x80000000;

  JTAG_AllowTAPReset = 1; // J-Link is allowed to use a TAP reset for JTAG-chain auto-detection

  // At the end of the JLINK_CORESIGHT_Configure(), the appropriate target interface switching
  // sequence is output.  This triggers a TAP reset on the target.  The IRPre, DRPre, IRPost, DRPost parameters describe
  // which device inside the JTAG chain is currently selected for communication.
  JLINK_CORESIGHT_Configure("IRPre=0;DRPre=0;IRPost=0;DRPost=0;IRLenDevice=4");
  //
  // Manually configure which APs are present on the CoreSight device
  //
  CORESIGHT_AddAP(0, CORESIGHT_APB_AP);
  CORESIGHT_AddAP(1, CORESIGHT_APB_AP);
  CORESIGHT_AddAP(2, CORESIGHT_APB_AP);
  CORESIGHT_AddAP(3, CORESIGHT_APB_AP);

  // Pre-selects an AP as an APB-AP that J-Link uses for debug communication
  // (when connected to an ARM Cortex A/R device).
  CORESIGHT_IndexAPBAPToUse = 1; // Use the 1st APB device (note counting from 1)

//Report("Debug1");
  //JLINK_MEM_WriteU32(0x80000FB0, 0xC5ACCE55); // DBG_LOCKACCESS
//Report("Debug2");
  //JLINK_MEM_WriteU32(0x8000002C, 0); // DBG_DSMCR
//Report("Debug3");
  v = JLINK_MEM_ReadU32(0x80000088); // DBG_DSCR
//Report("Debug4");
  v |= (7 << 13); // MDBGen, HDBGen, ITen
  JLINK_MEM_WriteU32(0x80000088, v);

}