Hi,

OT but possibly interesting for other people: I solved the previous problem with the JTAG where it didn't connect at all, apparently there are some electrical differences between the xilinx platform cable USB II and the Segger Flasher ARM so that the second one didn't work on the custom board. 100 Ohm series resistors on the JTAG lines like there are on the zedboard fixed it.


Now I can successfully connect, write simple instructions to increment a register in a loop, set the PC and step and see the register value incrementing (as was suggested in another thread).

The next step is finally flashing the Flash memory, however I get this error

J-Link>loadbin C:\Users\Raffaele\Desktop\flash\BOOT.bin, 0xFC000000
Halting CPU for downloading file.
Downloading file [C:\Users\Raffaele\Desktop\flash\BOOT.bin]...

****** Error: Error while determining flash info (Bank @ 0xFC000000)
Unspecified error -1

My flash is N25Q256A11EF840E (1.8V) connected to the usual MIO pins. On a ZedBoard (which I bought as per your suggestion to ensure there were no problems upstream), I can flash no problem. It has a different flash obviously. I set the same pull-up/pull-down configuration on the zedboard (QSPI bootmode) and I can flash. But not on the custom board.

The error isn't very informative.

On the zedboard I get the expected result (I had flashed it previously with the same data)

J-Link>loadbin C:\Users\Raffaele\Desktop\project_1\project_1.sdk\BOOT.bin, 0xFC000000
Downloading file [C:\Users\Raffaele\Desktop\project_1\project_1.sdk\BOOT.bin]...
J-Link: Flash download: Bank 0 @ 0xFC000000: Skipped. Contents already matchO.K.

Thank you for your help. I can setup the tunneling thing if you think that will help get more information.

Hi Nino,

I understand.

Does the answer about the license posted by Niklas in this thread forum.segger.com/index.php?page=Thread&threadID=4102 still hold?

Also, while the template works and is a good starting point, it would be easier for me if the code of an actual implementation of Open Flash Loader was available as an example, all I can find is compiled files or just dummy template code.

Is it possible to have the source code for the zedboard implementation or if not, any other example?

Thank you.

Hi nino,

one chip is connected on pins from MIO1 to MIO6 the same as on the zeboard, a second chip is connected with the DQ pins to MIO10-MIO13 (in numerical order) plus CS on the pin MIO0 and CLK on MIO9.

The segger is connected to the jtag port of the Zynq.

With the xilinx tools I choose n25q256-qspi-x8-dual_parallel or mt25qu256-qspi-x8-dual_parallel (for the newer version, 2017.4) as "configuration memory device" if that information is of any help.

Thank you for your help.

Hi, I'm attaching the relevant part of the schematic.

Thank you for your assistance.

Hi Nino,

I understand. I will try making it work with only the first flash.

To make a decision on the way forward, we'd need a quote (without any committment for now) for option 2 listing price/conditions.
You can send it to the e-mail I used to register to the forum.

by the way, I tried it and I get the same error as in the title even when the second flash chip and its CS pull-up resistor are not soldered to the board, with the xilinx tools it works with just one chip too.