I am trying to upload this simple assembly program:
.global _start
.text _start:
mov r0, #0
mov r1, #1
increase:
add r0, r0, r1
cmp r0, #10
bne increase
decrease:
sub r0, r0, r1
cmp r0, #0
bne decrease
b increase
stop: b stop
to my LPC4088 (I am using Embedded artists LPC4088 QSB) via JLink so I could later debug it. First I compiled my sources with all the debugging symbols using GCC toolchain:
arm-none-eabi-as -g -gdwarf-2 -o program.o program.s
arm-none-eabi-ld -Ttext=0x0 -o program.elf program.o
arm-none-eabi-objcopy -O binary program.elf program.bin
I then opened application JLinkExe. In application's terminal I powered on my board using power on, I connected to the Cortex-M4 using command connect and uploaded my binaries using loadbin program.bin 0x0 which should download this into target's FLASH memory located at 0x0. At last I set the program counter to start at the beginning SetPC 0x4.
But when I start debugging using step command s I get commands that I haven't even used in my source file...
This is the whole procedure inside JLinkExe terminal:
J-Link>power on
J-Link>connect
Device "CORTEX-M4" selected.
Connecting to target via JTAG
TotalIRLen = 4, IRPrint = 0x01
JTAG chain detection found 1 devices:
#0 Id: 0x4BA00477, IRLen: 04, CoreSight JTAG-DP
Scanning AP map to find all available APs
AP[1]: Stopped AP scan as end of AP map has been reached
AP[0]: AHB-AP (IDR: 0x24770011)
Iterating through AP map to find AHB-AP to use
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FF000
CPUID register: 0x410FC241. Implementer code: 0x41 (ARM)
Found Cortex-M4 r0p1, Little endian.
FPUnit: 6 code (BP) slots and 2 literal slots
CoreSight components:
ROMTbl[0] @ E00FF000
ROMTbl[0][0]: E000E000, CID: B105E00D, PID: 000BB00C SCS-M7
ROMTbl[0][1]: E0001000, CID: B105E00D, PID: 003BB002 DWT
ROMTbl[0][2]: E0002000, CID: B105E00D, PID: 002BB003 FPB
ROMTbl[0][3]: E0000000, CID: B105E00D, PID: 003BB001 ITM
ROMTbl[0][4]: E0040000, CID: B105900D, PID: 000BB9A1 TPIU
ROMTbl[0][5]: E0041000, CID: B105900D, PID: 000BB925 ETM
Cortex-M4 identified.
J-Link>loadbin program.bin 0x0
Halting CPU for downloading file.
Downloading file [program.bin]...
O.K.
J-Link>SetPC 0x4
J-Link>s
00000004: 1D 00 MOVS R5, R3
J-Link>s
00000006: FF 1F SUBS R7, R7, #7
J-Link>s
00000008: E1 00 LSLS R1, R4, #3
J-Link>s
0000000A: FF 1F SUBS R7, R7, #7
J-Link>s
0000000C: E3 00 LSLS R3, R4, #3
J-Link>s
0000000E: FF 1F SUBS R7, R7, #7
J-Link>s
00000010: E5 00 LSLS R5, R4, #3
J-Link>s
00000012: FF 1F SUBS R7, R7, #7
J-Link>s
00000014: E7 00 LSLS R7, R4, #3
J-Link>
So this code must have come from somewhere and it may be the LPC4088's Boot ROM which is remapped to 0x0 at boot time as is stated on page 907 of the LPC4088 user manual :
[img]https://i.stack.imgur.com/3hkhH.png[/img]
Do you have any idea on how to overcome this Boot ROM problem, so I could debug my program normally? Is it possible to somehow use register MEMMAP described above?
.global _start
.text _start:
mov r0, #0
mov r1, #1
increase:
add r0, r0, r1
cmp r0, #10
bne increase
decrease:
sub r0, r0, r1
cmp r0, #0
bne decrease
b increase
stop: b stop
to my LPC4088 (I am using Embedded artists LPC4088 QSB) via JLink so I could later debug it. First I compiled my sources with all the debugging symbols using GCC toolchain:
arm-none-eabi-as -g -gdwarf-2 -o program.o program.s
arm-none-eabi-ld -Ttext=0x0 -o program.elf program.o
arm-none-eabi-objcopy -O binary program.elf program.bin
I then opened application JLinkExe. In application's terminal I powered on my board using power on, I connected to the Cortex-M4 using command connect and uploaded my binaries using loadbin program.bin 0x0 which should download this into target's FLASH memory located at 0x0. At last I set the program counter to start at the beginning SetPC 0x4.
But when I start debugging using step command s I get commands that I haven't even used in my source file...
This is the whole procedure inside JLinkExe terminal:
J-Link>power on
J-Link>connect
Device "CORTEX-M4" selected.
Connecting to target via JTAG
TotalIRLen = 4, IRPrint = 0x01
JTAG chain detection found 1 devices:
#0 Id: 0x4BA00477, IRLen: 04, CoreSight JTAG-DP
Scanning AP map to find all available APs
AP[1]: Stopped AP scan as end of AP map has been reached
AP[0]: AHB-AP (IDR: 0x24770011)
Iterating through AP map to find AHB-AP to use
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FF000
CPUID register: 0x410FC241. Implementer code: 0x41 (ARM)
Found Cortex-M4 r0p1, Little endian.
FPUnit: 6 code (BP) slots and 2 literal slots
CoreSight components:
ROMTbl[0] @ E00FF000
ROMTbl[0][0]: E000E000, CID: B105E00D, PID: 000BB00C SCS-M7
ROMTbl[0][1]: E0001000, CID: B105E00D, PID: 003BB002 DWT
ROMTbl[0][2]: E0002000, CID: B105E00D, PID: 002BB003 FPB
ROMTbl[0][3]: E0000000, CID: B105E00D, PID: 003BB001 ITM
ROMTbl[0][4]: E0040000, CID: B105900D, PID: 000BB9A1 TPIU
ROMTbl[0][5]: E0041000, CID: B105900D, PID: 000BB925 ETM
Cortex-M4 identified.
J-Link>loadbin program.bin 0x0
Halting CPU for downloading file.
Downloading file [program.bin]...
O.K.
J-Link>SetPC 0x4
J-Link>s
00000004: 1D 00 MOVS R5, R3
J-Link>s
00000006: FF 1F SUBS R7, R7, #7
J-Link>s
00000008: E1 00 LSLS R1, R4, #3
J-Link>s
0000000A: FF 1F SUBS R7, R7, #7
J-Link>s
0000000C: E3 00 LSLS R3, R4, #3
J-Link>s
0000000E: FF 1F SUBS R7, R7, #7
J-Link>s
00000010: E5 00 LSLS R5, R4, #3
J-Link>s
00000012: FF 1F SUBS R7, R7, #7
J-Link>s
00000014: E7 00 LSLS R7, R4, #3
J-Link>
So this code must have come from somewhere and it may be the LPC4088's Boot ROM which is remapped to 0x0 at boot time as is stated on page 907 of the LPC4088 user manual :
[img]https://i.stack.imgur.com/3hkhH.png[/img]
Do you have any idea on how to overcome this Boot ROM problem, so I could debug my program normally? Is it possible to somehow use register MEMMAP described above?
The post was edited 4 times, last by 71GA ().