[ABANDONED] can not connect to Cortex-R5 2cores

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  • [ABANDONED] can not connect to Cortex-R5 2cores

    I need help.
    I can not connect to Cortex-R5 2cores.

    J-Link>connect
    Device>?
    'Target device settings' window.

    If I then select Cortex-R5 from the 'Core' drop down list, however none of them has more than 1 core as shown under 'NumCores' column.
    Can you tell me which one variant I need to use for multicore debuging?
    If I select 'Unspecified Cortex-R5' I can connect to core 0.
    However, 'CoreSight AP [1]' does not appear.

    I'd like to try out ....
    If core1 does not appear in the JTAG chain unless you set something on core0, what is the procedure?

    Run core0.axf with Ozone => J-Link Commander 'connect' ??


    [log]
    SEGGER J-Link Commander V6.22f (Compiled Jan 12 2018 16:18:39)
    DLL version V6.22f, compiled Jan 12 2018 16:18:01

    Connecting to J-Link via USB...O.K.
    Firmware: J-Link Ultra V4 compiled Jan 11 2018 10:41:15
    Hardware version: V4.00
    S/N: 504404285
    License(s): RDI, FlashBP, FlashDL, JFlash, GDB
    VTref = 1.822V

    Type "connect" to establish a target connection, '?' for help
    J-Link>connect
    Please specify device / core. <Default>: CORTEX-R5
    Type '?' for selection dialog
    Device>
    Please specify target interface:
    J) JTAG (Default)
    S) SWD
    TIF>s
    Specify target interface speed [kHz]. <Default>: 4000 kHz
    Speed>
    Device "CORTEX-R5" selected.


    Connecting to target via SWD
    Found SW-DP with ID 0x6BA02477
    CoreSight AP[0]: 0x54770002, APB-AP
    ROMTbl 0 [0]: 00020003, CID: B105100D, PID:04-000BB4B1 ROM Table
    ROMTbl 1 [0]: 00010003, CID: B105900D, PID:04-004BBC15 Cortex-R5
    Found Cortex-R5 r1p3
    4 code breakpoints, 3 data breakpoints
    Debug architecture ARMv7.0
    Data endian: little
    Main ID register: 0x411FC153
    I-Cache L1: 16 KB, 128 Sets, 32 Bytes/Line, 4-Way
    D-Cache L1: 16 KB, 128 Sets, 32 Bytes/Line, 4-Way
    TCM Type register: 0x00010001
    MPU Type register: 0x00000C00
    System control register:
    Instruction endian: little
    Level-1 instruction cache enabled
    Level-1 data cache enabled
    MPU enabled
    Branch prediction enabled
    Cortex-R5 identified.
    J-Link>

  • Hello,

    Thank you for your inquiry.
    Which device are you trying to connect to?
    Is it supported by J-Link?
    The general R5 architecture is supported but when trying to connect to multi-core devices special handlings are most likely needed.
    You can add support for new devices yourself: wiki.segger.com/Adding_Support_for_New_Devices

    So far for all multi core devices special connect handlings were required. To do this you can use a JLinkScript file. How is described in the J-Link user manual.
    Mostly other cores need to be "enabled" through core 0 first before you can connect to them.

    Best regards,
    Nino
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/
    Or you can contact us via e-mail.

  • Thanks for the reply.
    Generally it is not a sale SoC, I can write detailed information here because of the contract with me and my customers.
    If I can not understand the manual carefully, I will consult with my customer and write again.