Hello,
we have been using J-Link to debug MCIMX6G1 since it's support was introduced without any issues. We have been running Win 7, but unfortunately, we're forced to move to Win 10. We have already found two issues.
The first issue is with fw upgrade. When firmware upgrade attempt occurs, it fails almost immediately (see attached image ). Luckily unplugging and plugging J-link again solves the issue, as the fw upgrade from "recovery mode" works.
Second issue is that new versions (6.21d, 6.22, 6.22a) couldn't attach to cpu any more. Log follows. The result is same for any fw version we tried.
Display All
But, if we use older J-Link version (6.15f), it works as expected even with newest firmware:
Display All
Although we eventualy got working configuration, it doesn't somehow feel good, to ignore these issues.
we have been using J-Link to debug MCIMX6G1 since it's support was introduced without any issues. We have been running Win 7, but unfortunately, we're forced to move to Win 10. We have already found two issues.
The first issue is with fw upgrade. When firmware upgrade attempt occurs, it fails almost immediately (see attached image ). Luckily unplugging and plugging J-link again solves the issue, as the fw upgrade from "recovery mode" works.
Second issue is that new versions (6.21d, 6.22, 6.22a) couldn't attach to cpu any more. Log follows. The result is same for any fw version we tried.
C Source Code
- C:\Program Files (x86)\SEGGER\JLink_V622a>jlink
- SEGGER J-Link Commander V6.22a (Compiled Nov 28 2017 17:56:48)
- DLL version V6.22a, compiled Nov 28 2017 17:56:10
- Connecting to J-Link via USB...O.K.
- Firmware: J-Link Pro V4 compiled Nov 28 2017 11:47:28
- Hardware version: V4.00
- S/N: 174xxxxxx
- License(s): RDI, FlashBP, FlashDL, JFlash, GDB
- IP-Addr: DHCP (no addr. received yet)
- VTref = 1.089V
- Type "connect" to establish a target connection, '?' for help
- J-Link>connect
- Please specify device / core. <Default>: MCIMX6G1
- Type '?' for selection dialog
- Device>
- Please specify target interface:
- J) JTAG (Default)
- S) SWD
- TIF>
- Device position in JTAG chain (IRPre,DRPre) <Default>: -1,-1 => Auto-detect
- JTAGConf>
- Specify target interface speed [kHz]. <Default>: 4000 kHz
- Speed>
- Device "MCIMX6G1" selected.
- Connecting to target via JTAG
- TotalIRLen = 13, IRPrint = 0x0101
- **************************
- WARNING: At least one of the connected devices is not JTAG compliant (IEEE Std 1149.1, 7.1.1.d, IR-cells). (NumDevices = 3, NumBitsSet = 2)
- **************************
- JTAG chain detection found 3 devices:
- #0 Id: 0x5BA00477, IRLen: 04, CoreSight JTAG-DP
- #1 Id: 0x00000001, IRLen: 05, Unknown device
- #2 Id: 0x1891D01D, IRLen: 04, JTAG-DP
- Scanning AP map to find all available APs
- AP[2]: Stopped AP scan as end of AP map seems to be reached
- AP[0]: AHB-AP (IDR: 0x74770001)
- AP[1]: APB-AP (IDR: 0x44770002)
- Iterating through AP map to find AHB-AP to use
- AP[0]: Skipped. Not an APB-AP
- AP[1]: APB-AP found
- Invalid ROM table component ID 0x2F0F0F02 @ 0x20001EF0 (expected 0xB105100D). Trying again at alternative offset.
- Invalid ROM table component ID 0x2F0F0F02 @ 0x60000FF0 (expected 0xB105100D). Trying again at alternative offset.
- TotalIRLen = 13, IRPrint = 0x0101
- **************************
- WARNING: At least one of the connected devices is not JTAG compliant (IEEE Std 1149.1, 7.1.1.d, IR-cells). (NumDevices = 3, NumBitsSet = 2)
- **************************
- JTAG chain detection found 3 devices:
- #0 Id: 0x5BA00477, IRLen: 04, CoreSight JTAG-DP
- #1 Id: 0x00000001, IRLen: 05, Unknown device
- #2 Id: 0x1891D01D, IRLen: 04, JTAG-DP
- ****** Error: Cortex-A/R-JTAG (connect): Could not determine address of core debug registers. Incorrect CoreSight ROM table in device?
- TotalIRLen = 13, IRPrint = 0x0101
- **************************
- WARNING: At least one of the connected devices is not JTAG compliant (IEEE Std 1149.1, 7.1.1.d, IR-cells). (NumDevices = 3, NumBitsSet = 2)
- **************************
- JTAG chain detection found 3 devices:
- #0 Id: 0x5BA00477, IRLen: 04, CoreSight JTAG-DP
- #1 Id: 0x00000001, IRLen: 05, Unknown device
- #2 Id: 0x1891D01D, IRLen: 04, JTAG-DP
- TotalIRLen = 13, IRPrint = 0x0101
- **************************
- WARNING: At least one of the connected devices is not JTAG compliant (IEEE Std 1149.1, 7.1.1.d, IR-cells). (NumDevices = 3, NumBitsSet = 2)
- **************************
- JTAG chain detection found 3 devices:
- #0 Id: 0x5BA00477, IRLen: 04, CoreSight JTAG-DP
- #1 Id: 0x00000001, IRLen: 05, Unknown device
- #2 Id: 0x1891D01D, IRLen: 04, JTAG-DP
- Cannot connect to target.
But, if we use older J-Link version (6.15f), it works as expected even with newest firmware:
C Source Code
- J-Link>connect
- Please specify device / core. <Default>: MCIMX6G1
- Type '?' for selection dialog
- Device>
- Please specify target interface:
- J) JTAG (Default)
- S) SWD
- TIF>
- Device position in JTAG chain (IRPre,DRPre) <Default>: -1,-1 => Auto-detect
- JTAGConf>
- Specify target interface speed [kHz]. <Default>: 4000 kHz
- Speed>
- Device "MCIMX6G1" selected.
- TotalIRLen = 13, IRPrint = 0x0101
- **************************
- WARNING: At least one of the connected devices is not JTAG compliant (IEEE Std 1149.1, 7.1.1.d, IR-cells). (NumDevices = 3, NumBitsSet = 2)
- **************************
- JTAG chain detection found 3 devices:
- #0 Id: 0x5BA00477, IRLen: 04, CoreSight JTAG-DP
- #1 Id: 0x00000001, IRLen: ?, Unknown device
- #2 Id: 0x1891D01D, IRLen: ?, Unknown device
- ARM AP[0]: 0x74770001, AHB-AP
- ARM AP[1]: 0x44770002, APB-AP
- ROMTbl[0][0]: CompAddr: 80001000 CID: B105900D, PID:04-001BB961 TMC
- ROMTbl[0][1]: CompAddr: 80002000 CID: B105900D, PID:04-004BB906 ECT / CTI
- ROMTbl[0][2]: CompAddr: 80003000 CID: B105900D, PID:04-004BB912 TPIU
- ROMTbl[0][3]: CompAddr: 80004000 CID: B105F00D, PID:04-001BB101
- ROMTbl[0][4]: CompAddr: 80020000 CID: B105100D, PID:04-000BB4A7 ROM Table
- ROMTbl[1][0]: CompAddr: 80030000 CID: B105900D, PID:04-005BBC07 Cortex-A7
- Found Cortex-A7 r0p5
- 6 code breakpoints, 4 data breakpoints
- Debug architecture ARMv7.1
- Data endian: little
- Main ID register: 0x410FC075
- I-Cache L1: 32 KB, 512 Sets, 32 Bytes/Line, 2-Way
- D-Cache L1: 32 KB, 128 Sets, 64 Bytes/Line, 4-Way
- Unified-Cache L2: 128 KB, 256 Sets, 64 Bytes/Line, 8-Way
- System control register:
- Instruction endian: little
- Level-1 instruction cache enabled
- Level-1 data cache enabled
- MMU enabled
- Branch prediction enabled
- Cortex-A7 identified.
- J-Link>
Although we eventualy got working configuration, it doesn't somehow feel good, to ignore these issues.
The post was edited 1 time, last by jiri ().