[ABANDONED] j-Link can't halt the Cortex-M3 CPU

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  • [ABANDONED] j-Link can't halt the Cortex-M3 CPU

    I am working with OnSemi RSL10 Bluetooth chip which has ARM Cortex-M3 core. For some reason, after I flashed it with a firmware it keeps crashing and resetting. I am trying to get it halt so I can download a new image into it, but in noway J-link can halt the CPU. I tried r,h, setpc to an address, but none work. It always display ***Can't Halt CPU***
    Can you please help with this? Here is a sample run with J-Link commander.


    J-Link>h


    **************************
    WARNING: CPU could not be halted
    **************************


    J-Link>r
    Reset delay: 0 ms
    Reset type NORMAL: Resets core & peripherals via SYSRESETREQ & VECTRESET bit.
    Reset: Halt core after reset via DEMCR.VC_CORERESET.
    Reset: Reset device via AIRCR.SYSRESETREQ.
    Reset: SYSRESETREQ has confused core.
    Found SW-DP with ID 0x2BA01477
    AP map detection skipped. User manually configured AP map.
    AP[0]: AHB-AP (IDR: Not set)
    AP[0]: Core found
    AP[0]: AHB-AP ROM base: 0xE00FF000
    CPUID register: 0x412FC231. Implementer code: 0x41 (ARM)
    Found Cortex-M3 r2p1, Little endian.
    Reset: Using fallback: VECTRESET.
    Reset: Halt core after reset via DEMCR.VC_CORERESET.
    Reset: Reset device via AIRCR.VECTRESET.
    Reset: VECTRESET has confused core.
    Reset: Using fallback: Reset pin.
    Reset: Halt core after reset via DEMCR.VC_CORERESET.
    Reset: Reset device via reset pin
    Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
    Reset: Reconnecting and manually halting CPU.
    Found SW-DP with ID 0x2BA01477
    AP map detection skipped. User manually configured AP map.
    AP[0]: AHB-AP (IDR: Not set)
    AP[0]: Skipped. Could not read AHB ROM register


    **************************
    WARNING: CPU could not be halted
    **************************


    Reset: Core did not halt after reset, trying to disable WDT.
    Reset: Halt core after reset via DEMCR.VC_CORERESET.
    Reset: Reset device via reset pin
    Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
    Reset: Reconnecting and manually halting CPU.
    Found SW-DP with ID 0x2BA01477


    **************************
    WARNING: CPU could not be halted
    **************************


    Reset: Failed. Toggling reset pin and trying reset strategy again.
    Reset: Halt core after reset via DEMCR.VC_CORERESET.
    Reset: Reset device via AIRCR.SYSRESETREQ.
    Reset: SYSRESETREQ has confused core.
    Found SW-DP with ID 0x2BA01477
    AP map detection skipped. User manually configured AP map.
    AP[0]: AHB-AP (IDR: Not set)
    AP[0]: Core found
    AP[0]: AHB-AP ROM base: 0xE00FF000
    CPUID register: 0x412FC231. Implementer code: 0x41 (ARM)
    Found Cortex-M3 r2p1, Little endian.
    Reset: Using fallback: VECTRESET.
    Reset: Halt core after reset via DEMCR.VC_CORERESET.
    Reset: Reset device via AIRCR.VECTRESET.
    Reset: VECTRESET has confused core.
    Reset: Using fallback: Reset pin.
    Reset: Halt core after reset via DEMCR.VC_CORERESET.
    Reset: Reset device via reset pin
    Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
    Reset: Reconnecting and manually halting CPU.
    Found SW-DP with ID 0x2BA01477
    AP map detection skipped. User manually configured AP map.
    AP[0]: AHB-AP (IDR: Not set)
    AP[0]: Skipped. Could not read AHB ROM register


    **************************
    WARNING: CPU could not be halted
    **************************


    Reset: Core did not halt after reset, trying to disable WDT.
    Reset: Halt core after reset via DEMCR.VC_CORERESET.
    Reset: Reset device via reset pin
    Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
    Reset: Reconnecting and manually halting CPU.
    Found SW-DP with ID 0x2BA01477
    AP map detection skipped. User manually configured AP map.
    AP[0]: AHB-AP (IDR: Not set)
    AP[0]: Skipped. Could not read AHB ROM register


    **************************
    WARNING: CPU could not be halted
    **************************
  • Hi,


    I could not reproduce any issue with an empty device / generic target application.
    Can you provide is with a target application in order to reproduce the issue?
    Do you use low power modes in the application?
    Does the target application constrain the debug unit of the target device in any way?

    Best regards,
    Niklas
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