Hi,

I modified a imx6ULL EVK per: wiki.segger.com/IMX6UL-EVK (there's a imx6UL EVK and a imx6ULL EVK, but I believe these modifications will work as they appear to use the same baseboard).
JLink Commander gives a "can't halt after reset" message regardless if I use a reset delay and trying different JTAG options.

NOTE: I can use a "halt" after the reset attempt, but JFLASH wouldn't allow any operations after popping up "Bad JTAG communication: Write to IR: Expected 0x1, got 0xF (TAP Command: 10) @ Off 0x5. Failed to connect. Could not perform custom init sequence."

Here's sample of the JLink session:

Segger JLINK 6.18D 9/2/17 Problem:
SEGGER J-Link Commander V6.18d (Compiled Sep 1 2017 18:30:35)
DLL version V6.18d, compiled Sep 1 2017 18:29:59

Connecting to J-Link via USB...O.K.
Firmware: J-Link ARM-Pro V3.x compiled Jun 6 2014 16:00:09
Hardware version: V3.00
S/N: 173000640
License(s): RDI, FlashBP, FlashDL, JFlash, GDB
IP-Addr: DHCP (no addr. received yet)
VTref = 0.000V

Type "connect" to establish a target connection,
'?' for help

J-Link>connect

Please specify device / core. <Default>: MCIMX6Y2
Type '?' for selection dialog
Device>
Please specify target interface:
J) JTAG (Default)
S) SWD
TIF>
Device position in JTAG chain (IRPre,DRPre)
<Default>: -1,-1 => Auto-detect
JTAGConf>
Specify target interface speed [kHz]. <Default>: 4000
kHz
Speed>
Device "MCIMX6Y2" selected.


Connecting to target via JTAG
TotalIRLen = 13, IRPrint = 0x0101
**************************
WARNING: At least one of the connected devices is not JTAG
compliant (IEEE Std 1
149.1, 7.1.1.d, IR-cells). (NumDevices = 3, NumBitsSet = 2)
**************************
JTAG chain detection found 3 devices:
#0 Id: 0x5BA00477,
IRLen: 04, CoreSight JTAG-DP
#1 Id: 0x00000001,
IRLen: ?, Unknown device
#2 Id: 0x088C101D,
IRLen: ?, Unknown device
ARM AP[0]: 0x74770001, AHB-AP
ARM AP[1]: 0x44770002, APB-AP
ROMTbl[0][0]: CompAddr: 80001000 CID: B105900D,ID:04-001BB961 TMC
ROMTbl[0][1]: CompAddr: 80002000 CID: B105900D,PID:04-004BB906 ECT / CTI
ROMTbl[0][2]: CompAddr: 80003000 CID: B105900D,PID:04-004BB912 TPIU
ROMTbl[0][3]: CompAddr: 80004000 CID: B105F00D,PID:04-001BB101 ???
ROMTbl[0][4]: CompAddr: 80020000 CID: B105100D,PID:04-000BB4A7 ROM Table
ROMTbl[1][0]: CompAddr: 80030000 CID: B105900D,PID:04-005BBC07 Cortex-A7

Found Cortex-A7 r0p5
6 code breakpoints, 4 data breakpoints
Debug architecture ARMv7.1
Data endian: little
Main ID register: 0x410FC075
I-Cache L1: 32 KB, 512 Sets, 32 Bytes/Line, 2-Way
D-Cache L1: 32 KB, 128 Sets, 64 Bytes/Line, 4-Way
Unified-Cache L2: 128 KB, 256 Sets, 64 Bytes/Line, 8-Way
System control register:
Instruction endian:little
Level-1 instruction cache enabled
Level-1 data cache disabled
MMU disabled
Branch prediction enabled
Cortex-A7 identified.

J-Link>r
Reset delay: 0 ms
Reset type NORMAL: Toggle reset pin and halt CPU core.
Cortex-A/R (reset): Re-initializing debug logic.
**************************
WARNING: CPU not halted after Reset, halting using Halt request
**************************

****** Error: Bad JTAG communication: Write to IR: Expected 0x1, got 0xF (TAP Command : 10) @ Off 0x5.


Any help would be appreciated.

Geoffrey

SWD is not supported on iMX6ULL.

Both the iMX6UL EVK and iMX6ULL EVKs use the same base board. The JTAG sections in their respective schematics are identical.

Yes, you are correct and I may have turned on the power after initiating JLINK. Here's another run showing VTref with ~3.0V with the EVK board power guaranteed on.

SEGGER J-Link Commander V6.18a (Compiled Aug 11 2017 17:53:56)
DLL version V6.18a, compiled Aug 11 2017 17:53:19

Connecting to J-Link via USB...O.K.
Firmware: J-Link ARM-Pro V3.x compiled Jun 6 2014 16:00:09
Hardware version: V3.00
S/N: 173000640
License(s): RDI, FlashBP, FlashDL, JFlash, GDB
IP-Addr: DHCP (no addr. received yet)
VTref = 3.073V


Type "connect" to establish a target connection, '?' for help
J-Link>connect
Please specify device / core. <Default>: MCIMX6Y2
Type '?' for selection dialog
Device>
Please specify target interface:
J) JTAG (Default)
S) SWD
TIF>
Device position in JTAG chain (IRPre,DRPre) <Default>: -1,-1 => Auto-detect
JTAGConf>
Specify target interface speed [kHz]. <Default>: 4000 kHz
Speed>
Device "MCIMX6Y2" selected.


Connecting to target via JTAG
TotalIRLen = 13, IRPrint = 0x0101

**************************
WARNING: At least one of the connected devices is not JTAG compliant (IEEE Std 1
149.1, 7.1.1.d, IR-cells). (NumDevices = 3, NumBitsSet = 2)

**************************

JTAG chain detection found 3 devices:
#0 Id: 0x5BA00477, IRLen: 04, CoreSight JTAG-DP
#1 Id: 0x00000001, IRLen: ?, Unknown device
#2 Id: 0x088C101D, IRLen: ?, Unknown device
ARM AP[0]: 0x74770001, AHB-AP
ARM AP[1]: 0x44770002, APB-AP
ROMTbl[0][0]: CompAddr: 80001000 CID: B105900D, PID:04-001BB961 TMC
ROMTbl[0][1]: CompAddr: 80002000 CID: B105900D, PID:04-004BB906 ECT / CTI
ROMTbl[0][2]: CompAddr: 80003000 CID: B105900D, PID:04-004BB912 TPIU
ROMTbl[0][3]: CompAddr: 80004000 CID: B105F00D, PID:04-001BB101 ???
ROMTbl[0][4]: CompAddr: 80020000 CID: B105100D, PID:04-000BB4A7 ROM Table
ROMTbl[1][0]: CompAddr: 80030000 CID: B105900D, PID:04-005BBC07 Cortex-A7
Found Cortex-A7 r0p5
6 code breakpoints, 4 data breakpoints
Debug architecture ARMv7.1
Data endian: little
Main ID register: 0x410FC075
I-Cache L1: 32 KB, 512 Sets, 32 Bytes/Line, 2-Way
D-Cache L1: 32 KB, 128 Sets, 64 Bytes/Line, 4-Way
Unified-Cache L2: 128 KB, 256 Sets, 64 Bytes/Line, 8-Way
System control register:
Instruction endian: little
Level-1 instruction cache enabled
Level-1 data cache disabled
MMU disabled
Branch prediction enabled
Cortex-A7 identified.
J-Link>r
Reset delay: 0 ms
Reset type NORMAL: Toggle reset pin and halt CPU core.
Cortex-A/R (reset): Re-initializing debug logic.

**************************
WARNING: CPU not halted after Reset, halting using Halt request
**************************


****** Error: Bad JTAG communication: Write to IR: Expected 0x1, got 0xF (TAP Co
mmand : 10) @ Off 0x5.

J-Link>halt
PC: (R15) = 000085CC, CPSR = 400001F3 (SVC mode, THUMB FIQ dis. IRQ dis.)
Current:
R0 =00000000, R1 =00900A30, R2 =10000000, R3 =00000800
R4 =00000000, R5 =00000002, R6 =00900BA4, R7 =02020000
R8 =000085D0, R9 =000085D0, R10=021E8000, R11=0001C200, R12=000100A1
R13=00000000, R14=020E0014, SPSR=0091FF64
USR: R8 =021E8000, R9 =0001C200, R10=000100A1, R11=00000000, R12=020E0014
R13=EB29E8A2, R14=E997F064
FIQ: R8 =9835A84E, R9 =59400E52, R10=C8E2C909, R11=4A859153, R12=EA074920
R13=88D1F3A4, R14=74A36414, SPSR=5C001206
IRQ: R13=144829B4, R14=0C22066F, SPSR=2702C4C0
SVC: R13=0091FF64, R14=00002F3B, SPSR=000001D3
ABT: R13=C15845E5, R14=E74260E5, SPSR=980E2851
UND: R13=039626A7, R14=FDC23888, SPSR=A4060100
J-Link>

Initially, just R1407 and R1431-4 were removed with the same results. Followed that with the addition R1912-4,6 according to the iMX6UL instructions with no change. I'll be buying another iMX6ULL EVK.

on another iMX6ULL EVK with R1407 and R1431-4 removed, the same "CPU not halted after Reset" occurred.

tried another Segger JLINKpro 4.00 with firmware upgraded to 9/1/17 with no change.

CM:
700-29364 REV A
SCH-29364 REV A
TR17120138

BB:
700-28616 REV A1
SCH-28616 REV C2
TR17112868

box:
MPN: MCIMX6ULL-EVK
LOT: A2TR171302
DTE: 1713
REV: A2

purchased several weeks ago