[SOLVED] TI device will not power on when connected to JLink TI 14-pin Adapter

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  • [SOLVED] TI device will not power on when connected to JLink TI 14-pin Adapter

    Hello,

    I am attempting to debug a target board with a TI DM3725 processor using the JLink Pro, but I am having issues when making connections from the board to the TI-14 Pin adapter. As previously stated, the device will not power on when all pins connected to ground are inserted into the adapter cable [pins: 4, 8, 10, 12]. The DM3725 is an ARM Cortex-A8, and should be supported by the JLink. Are there any issues with supporting the DM3725 specifically? Other Siatra processors (AM37XX) are supported and are similar to this one. I should mention that even when my device is connected to the adapter cable, and the adapter cable is not plugged into the Jlink Pro, the device will not power on. Power issues are occurring with connections to the adapter alone. The device operates as normal when not connected to the TI adapter.

    I've noticed that if and only if I remove 3 ground connections [specifically pins: 8, 10 & 12], the device will power on. In this case, Pin 4 (TDIS and Ground on the target), is still connected to the Adapter and to the JLINK Pro. The Jlink will then detect a very low voltage of about ~1.5V.


    When using JLink Commander, I see that the debugger detects a voltage reference of ~3.2 when all of the ground pins are inserted into the adapter; I believe the voltage reference for this board is 3.3v, so 3.2 volts is still a bit low. How can I resolve/debug this issue? Is it necessary to have all 4 connections to ground from the target board to the adapter?

    Thanks,
    OSS
  • Hi,


    I just gave it a try using a beagleboard with a DM3730 device and could not reproduce any issues.

    Source Code

    1. SEGGER J-Link Commander V6.18 (Compiled Aug 3 2017 16:19:59)
    2. DLL version V6.18, compiled Aug 3 2017 16:19:24
    3. Connecting to J-Link via USB...O.K.
    4. Firmware: J-Link Pro V4 compiled Jul 24 2017 17:06:05
    5. Hardware version: V4.00
    6. S/N: 174402383
    7. License(s): RDI, FlashBP, FlashDL, JFlash, GDB
    8. IP-Addr: DHCP (no addr. received yet)
    9. VTref = 1.803V
    10. Type "connect" to establish a target connection, '?' for help
    11. J-Link>con
    12. Please specify device / core. <Default>: LPC4367_M4
    13. Type '?' for selection dialog
    14. Device>dm3730
    15. Please specify target interface:
    16. J) JTAG (Default)
    17. S) SWD
    18. TIF>j
    19. Device position in JTAG chain (IRPre,DRPre) <Default>: -1,-1 => Auto-detect
    20. JTAGConf>
    21. Specify target interface speed [kHz]. <Default>: 4000 kHz
    22. Speed>
    23. Device "DM3730" selected.
    24. Connecting to target via JTAG
    25. InitTarget(): Initializing ICEPick
    26. TotalIRLen = 10, IRPrint = 0x0011
    27. JTAG chain detection found 2 devices:
    28. #0 Id: 0x0B6D602F, IRLen: 04, JTAG-DP
    29. #1 Id: 0x2B89102F, IRLen: 06, TI ICEPick
    30. ARM AP[0]: 0x14770001, AHB-AP
    31. ARM AP[1]: 0x04770002, APB-AP
    32. ROMTbl[0][0]: CompAddr: 54010000 CID: B105900D, PID:04-206BB921
    33. ROMTbl[0][1]: CompAddr: 54011000 CID: B105900D, PID:04-206BBC08 Cortex-A8
    34. Found Cortex-A8 r3p2
    35. 6 code breakpoints, 2 data breakpoints
    36. Debug architecture ARMv7.0
    37. Data endian: little
    38. Main ID register: 0x413FC082
    39. I-Cache L1: 32 KB, 128 Sets, 64 Bytes/Line, 4-Way
    40. D-Cache L1: 32 KB, 128 Sets, 64 Bytes/Line, 4-Way
    41. Unified-Cache L2: 256 KB, 512 Sets, 64 Bytes/Line, 8-Way
    42. System control register:
    43. Instruction endian: little
    44. Level-1 instruction cache enabled
    45. Level-1 data cache disabled
    46. MMU disabled
    47. Branch prediction enabled
    48. Cortex-A8 identified.
    49. J-Link>
    Display All


    What do you use? An evalbaord or custom hardware?

    Best regards,
    Niklas
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/

    Or you can contact us via e-mail.
  • Hi,

    Thanks for your response. I am debugging custom hw. I was able to resolve this issue; a ground loop was preventing power on/low voltage. I see that your version of the Jlink has support for the DM3730, but not for the DM3725. I was able to connect to my device using the AM3715 & the DM3730 as the base core. Is there any direct support for the DM3725 MCU?

    Source Code

    1. SEGGER J-Link Commander V6.18 (Compiled Aug 3 2017 16:19:59)
    2. DLL version V6.18, compiled Aug 3 2017 16:19:24
    3. Connecting to J-Link via USB...O.K.
    4. Firmware: J-Link Pro V4 compiled Jul 24 2017 17:06:05
    5. Hardware version: V4.00
    6. S/N: 174403100
    7. License(s): RDI, FlashBP, FlashDL, JFlash, GDB
    8. IP-Addr: DHCP (no addr. received yet)
    9. VTref = 3.304V
    10. Connecting to target via JTAG
    11. TotalIRLen = 6, IRPrint = 0x01
    12. AM35xx/37xx (connect): Adding core to JTAG chain.
    13. TotalIRLen = 10, IRPrint = 0x0011
    14. JTAG chain detection found 2 devices:
    15. #0 Id: 0x0B6D602F, IRLen: 04, JTAG-DP
    16. #1 Id: 0x2B89102F, IRLen: 06, TI ICEPick
    17. TotalIRLen = 10, IRPrint = 0x0011
    18. JTAG chain detection found 2 devices:
    19. #0 Id: 0x0B6D602F, IRLen: 04, JTAG-DP
    20. #1 Id: 0x2B89102F, IRLen: 06, TI ICEPick
    21. ARM AP[0]: 0x14770001, AHB-AP
    22. ARM AP[1]: 0x04770002, APB-AP
    23. ROMTbl[0][0]: CompAddr: 54010000 CID: B105900D, PID:04-206BB921
    24. ROMTbl[0][1]: CompAddr: 54011000 CID: B105900D, PID:04-206BBC08 Cortex-A8
    25. Found Cortex-A8 r3p2
    26. 6 code breakpoints, 2 data breakpoints
    27. Debug architecture ARMv7.0
    28. Data endian: little
    29. Main ID register: 0x413FC082
    30. I-Cache L1: 32 KB, 128 Sets, 64 Bytes/Line, 4-Way
    31. D-Cache L1: 32 KB, 128 Sets, 64 Bytes/Line, 4-Way
    32. Unified-Cache L2: 256 KB, 512 Sets, 64 Bytes/Line, 8-Way
    33. System control register:
    34. Instruction endian: little
    35. Level-1 instruction cache enabled
    36. Level-1 data cache disabled
    37. MMU disabled
    38. Branch prediction enabled
    39. Cortex-A8 identified.
    Display All


    Thanks,

    OSS

    The post was edited 1 time, last by osscope23 ().

  • Hi,


    the device requires a special connect.
    The special connect has been implemented and tested using a DM3730 device,
    therefore we cannot add DM3725 to the list of supported devices without having the hardware here.

    In case you really need DM3725 to be added to the list:
    If you send us 1-2 sample boards which can stay at SEGGER for test and maintenance, we can add official support for the DM3725 target device.


    Best regards,
    Niklas
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/

    Or you can contact us via e-mail.