Programming QSPI flash on Zynq ZC702 eval board - JLink Plus

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  • Programming QSPI flash on Zynq ZC702 eval board - JLink Plus

    Hi,
    I'm currently trying to use a J-Link Plus to program the QSPI flash on the Xilinx ZC702 board.
    Using JFlash I've selected Zynq 7020 as the device and can connect to the target successfully.


    However if I attempt to program the flash then errors are reported as follows:-


    Programming target (255 bytes, 1 range) ...
    - Start of determining flash info (Bank 0 @ 0xFC000000)
    - ERROR: Timeout while checking target RAM, core does not stop. (PC = 0x00000004, CPSR = 0x0000019B, LR = 0x00000014)!
    - ERROR: Failed to prepare for programming.
    Failed to execute RAMCode for RAM check!
    - Error while determining flash info (Bank 0 @ 0xFC000000)
    - End of determining flash info
    - Flash bank info:
    - 1 * 16384 KB @ 0xFC000000
    - ERROR: Failed to program target

    This was generating 255 bytes of test data and then trying to program using the "Manual Programming" option.

    Also fails when trying to use JLink commander to program.

    What steps an I missing in order to program successfully?
    Although Zynq 7020 is listed as supported on the Segger website do I still need to manually add init steps to the JFlash project?

    JLink log and JFlash project are attached for reference.

    I'm successfully using the J-Link Plus for debugging over JTAG under Mentor Sourcery Codebench on the same target board.

    Thanks.
    Files
    • JLink.zip

      (26.4 kB, downloaded 460 times, last: )
    • zc702.jflash

      (1.59 kB, downloaded 605 times, last: )
  • Hi,


    - ERROR: Timeout while checking target RAM, core does not stop. (PC = 0x00000004, CPSR = 0x0000019B, LR = 0x00000014)!
    - ERROR: Failed to prepare for programming.
    Failed to execute RAMCode for RAM check!

    In the "MCU" tab of the J-Flash project settings, what RAM address & size is configured?
    Does it work if you reduce the amount of RAM used(e.g to 8 KB)?

    Best regards,
    Niklas
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/

    Or you can contact us via e-mail.
  • Hi Niklas,
    Address is 0 and size is 256KB
    I tried reducing to 8KB but operation still failed although error messages were slightly different - see below


    Programming target (255 bytes, 1 range) ...
    - Start of determining flash info (Bank 0 @ 0xFC000000)
    - Error while determining flash info (Bank 0 @ 0xFC000000)
    - End of determining flash info
    - Flash bank info:
    - 1 * 16384 KB @ 0xFC000000
    - 255 bytes could not be programmed.
    - Target programmed successfully - Completed after 0.083 sec

    Despite last entry saying success.

    Regards,
  • Hi,


    i just gave it a try on a Zync 7020 zedboard,
    but could not reproduce any issue after setting RAM to 8KB:

    Source Code

    1. Application log started
    2. - J-Flash V6.18 (J-Flash compiled Aug 3 2017 16:19:44)
    3. - JLinkARM.dll V6.18 (DLL compiled Aug 3 2017 16:19:24)
    4. Creating new project file [C:\Program Files (x86)\SEGGER\JLink_V618\Default.jflash] ...
    5. - New project created successfully
    6. Close project
    7. - Project closed
    8. Creating new project ...
    9. - New project created successfully
    10. Reading entire flash chip ...
    11. - Connecting ...
    12. - Connected successfully
    13. - 1 sector, 1 range, 0xFC000000 - 0xFCFFFFFF
    14. - Start of determining flash info (Bank 0 @ 0xFC000000)
    15. - End of determining flash info
    16. - Flash bank info:
    17. - 512 * 64 KB @ 0xFC000000
    18. - Start of preparing flash programming
    19. - End of preparing flash programming
    20. - Start of blank checking
    21. - End of blank checking
    22. - Start of blank checking
    23. - End of blank checking
    24. - Start of blank checking
    25. - End of blank checking
    26. - Start of blank checking
    27. - End of blank checking
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    276. - Start of restoring
    277. - End of restoring
    278. - Target memory read successfully. (16777216 bytes, 1 range) - Completed after 12.299 sec
    279. Generating test data ...
    280. - 1 of 1 sectors selected, 1 range, 0xFC000000 - 0xFC0000FF
    281. - Test data generated successfully. (256 bytes, 1 range) - Completed after 0.023 sec
    282. Checking if selected data fits into selected flash sectors.
    283. Programming and verifying target (256 bytes, 1 range) ...
    284. - Start of determining flash info (Bank 0 @ 0xFC000000)
    285. - End of determining flash info
    286. - Flash bank info:
    287. - 512 * 64 KB @ 0xFC000000
    288. - Start of preparing flash programming
    289. - End of preparing flash programming
    290. - Start of determining dirty areas in flash cache
    291. - End of determining dirty areas
    292. - CPU speed could not be measured.
    293. - Start of erasing sectors
    294. - Start of blank checking
    295. - End of blank checking
    296. - Erasing range 0xFC000000 - 0xFC00FFFF (001 Sector, 64 KB)
    297. - End of erasing sectors
    298. - Start of flash programming
    299. - Programming range 0xFC000000 - 0xFC00FFFF (001 Sector, 64 KB)
    300. - End of flash programming
    301. - Flash programming performed for 1 range (65536 bytes)
    302. - 0xFC000000 - 0xFC00FFFF (001 Sector, 64 KB)
    303. - Start of verifying flash
    304. - End of verifying flash
    305. - Start of restoring
    306. - End of restoring
    307. - Target programmed and verified successfully (CRC = 0x1F5BA2F2) - Completed after 2.085 sec
    Display All



    Since it works from Mentor Sourcery Codebench with J-Link for you, I am currently a little bit out of ideas....
    Do you have any further thoughts on this?

    Best regards,
    Niklas
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/

    Or you can contact us via e-mail.
  • Hi Nicklas,
    Could you share the .jflash file you used so I can compare?
    I'll ask a colleague to give it a try on another ZC702 board.

    When running under Sourcery Codebench I've not programmed the flash just debugged my application.

    Thanks
  • Just realised you've said "Zedboard" in your last reply.
    This is a different board from the ZC702 evaluation board.
    Any ideas whether it should work or what changes are required?

    "Zynq 7020" is the device type we've been instructed by Mentor to use under Sourcery Codebench so I'd assumed it would be the same under JFlash/JLink commander.
  • Hi,


    please find attached the J-Flash project I used.
    Its a auto-generated project, I just added the JTAG configuration via the "detect" option in the "Target Interface" tab of the project settings.


    Best regards,
    Niklas
    Files
    • Zynq7020.jflash

      (1.78 kB, downloaded 576 times, last: )
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/

    Or you can contact us via e-mail.
  • Hi Niklas,
    I tried with the JFlash project you provided and I was still unable to program the flash - I've attached the zipped JLink.log for this attempt.


    I also tried auto-generating a new project with address size as 8KB and the resulting project file was identical to yours apart from the ID for Device0 in the JTAG section as follows:-


    mine Device0_ID = 0x23727093


    yours Device0_ID = 0x03727093

    But I think this Device is for the Programmable Logic, i.e. FPGA, within the Zynq so should not matter.

    As I mentioned in an earlier post the Zedboard you'd tested with is a different board from the ZC702 eval board although they both share the same Zynq processor.
    Perhaps I need to make some modifications.

    Thanks.
    Files
    • JLink.zip

      (25.57 kB, downloaded 431 times, last: )
  • Hi,


    As I mentioned in an earlier post the Zedboard you'd tested with is a different board from the ZC702 eval board although they both share the same Zynq processor.
    Perhaps I need to make some modifications.

    Looking forward to hearing of your results!

    Are you refering to this board?
    xilinx.com/products/boards-and-kits/ek-z7-zc702-g.html

    Unfortunately we do not have this board in our collection of reference boards.

    Best regards,
    Niklas
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/

    Or you can contact us via e-mail.
  • Hi,

    I would suggest the following two tests using J-Link Commander (JLink.exe):

    1. Connect to target by executing >connect<

    2. Test if download to RAM works using the >testwspeed<
    testwspeed 0

    3. Test if executing code from RAM works
    This can be done by any routine, a most basic one would be:

    C Source Code

    1. 0x0000: 0xE2800001; // Loop: ADD R0, R0, #1
    2. 0x0004: 0xEAFFFFFD; // B(-2) --> Loop

    Memory can be writen using the >w4 <Addr>, <Data>< command.
    The commands >g<, >h<, >s< can be used for go, halt and step (or e.g the "TestHaltGo" command) in order to test if halt/go works and if the counter in R0 is incremented as expected.


    Best regards,
    Niklas
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/

    Or you can contact us via e-mail.
  • Hi Niklas,
    I was able to confirm that downloading to RAM and also executing from RAM both work for the target system.
    Output from JLink is pasted below.

    I understand the Zedboard has a different sized QSPI flash - could that be the reason?
    Also tried adding JFlash initialisation steps equivalent to the initialisation performed by the debugger under Source Codebench but still no luck.


    SEGGER J-Link Commander V6.18 (Compiled Aug 3 2017 16:19:59)
    DLL version V6.18, compiled Aug 3 2017 16:19:24

    Connecting to J-Link via USB...O.K.
    Firmware: J-Link V10 compiled Jul 28 2017 08:59:01
    Hardware version: V10.10
    S/N: 600104810
    License(s): RDI, FlashBP, FlashDL, JFlash, GDB
    VTref = 3.348V


    Type "connect" to establish a target connection, '?' for help
    J-Link>connect
    Please specify device / core. <Default>: ZYNQ 7020
    Type '?' for selection dialog
    Device>
    Please specify target interface:
    J) JTAG (Default)
    S) SWD
    TIF>
    Device position in JTAG chain (IRPre,DRPre) <Default>: -1,-1 => Auto-detect
    JTAGConf>
    Specify target interface speed [kHz]. <Default>: 4000 kHz
    Speed>
    Device "ZYNQ 7020" selected.


    Connecting to target via JTAG
    TotalIRLen = 10, IRPrint = 0x0051
    JTAG chain detection found 2 devices:
    #0 Id: 0x23727093, IRLen: 06, Unknown device
    #1 Id: 0x4BA00477, IRLen: 04, CoreSight JTAG-DP
    ARM AP[0]: 0x44770001, AHB-AP
    ARM AP[1]: 0x24770002, APB-AP
    ROMTbl[0][0]: CompAddr: 80001000 CID: B105900D, PID:04-003BB907 ETB
    ROMTbl[0][1]: CompAddr: 80002000 CID: B105900D, PID:04-002BB906 ECT / CTI
    ROMTbl[0][2]: CompAddr: 80003000 CID: B105900D, PID:04-004BB912 TPIU
    ROMTbl[0][3]: CompAddr: 80004000 CID: B105900D, PID:04-001BB908 CSTF
    ROMTbl[0][4]: CompAddr: 80005000 CID: B105900D, PID:04-002BB913 ITM
    ROMTbl[0][5]: CompAddr: 80009000 CID: B105900D, PID:04-002BB906 ECT / CTI
    ROMTbl[0][6]: CompAddr: 8000A000 CID: B105900D, PID:04-002BB906 ECT / CTI
    ROMTbl[0][7]: CompAddr: 8000B000 CID: B105900D, PID:00-000C9001
    ROMTbl[0][8]: CompAddr: 8000C000 CID: B105900D, PID:03-072893B2
    ROMTbl[0][9]: CompAddr: 80080000 CID: B105100D, PID:04-000BB4A9 ROM Table
    ROMTbl[1][0]: CompAddr: 80090000 CID: B105900D, PID:04-000BBC09 Cortex-A9
    Found Cortex-A9 r3p0
    6 code breakpoints, 4 data breakpoints
    Debug architecture ARMv7.0
    Data endian: little
    Main ID register: 0x413FC090
    I-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way
    D-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way
    System control register:
    Instruction endian: little
    Level-1 instruction cache disabled
    Level-1 data cache disabled
    MMU disabled
    Branch prediction disabled
    Cortex-A9 identified.
    J-Link>r
    Reset delay: 0 ms
    Reset type NORMAL: Toggle reset pin and halt CPU core.
    J-Link>h
    PC: (R15) = 00000000, CPSR = 900001DF (System mode, ARM FIQ dis. IRQ dis.)
    Current:
    R0 =F8007028, R1 =FFFFFFFF, R2 =4C00E07F, R3 =F8007000
    R4 =FFFFFF00, R5 =FFFFFF04, R6 =00000018, R7 =F8000004
    R8 =00000008, R9 =00000008, R10=0000767B, R11=E3E0F0D3, R12=F8000244
    R13=EA000049, R14=00000000
    USR: R8 =0000767B, R9 =E3E0F0D3, R10=F8000244, R11=EA000049, R12=00000000
    R13=E5801000, R14=00000000
    FIQ: R8 =00000000, R9 =00000000, R10=00000000, R11=00000000, R12=00000000
    R13=00000000, R14=00000000, SPSR=600F0051
    IRQ: R13=00000000, R14=00000000, SPSR=600F0052
    SVC: R13=00000000, R14=00000048, SPSR=600F0053
    ABT: R13=00000000, R14=00000000, SPSR=600F0057
    UND: R13=00000000, R14=00000000, SPSR=600F005B
    J-Link>wreg R0,0
    R0 = 0x00000000
    J-Link>SetPC 0
    J-Link>w4 0,e2800001
    Writing E2800001 -> 00000000
    J-Link>w4 4,eafffffd
    Writing EAFFFFFD -> 00000004
    J-Link>regs
    PC: (R15) = 00000000, CPSR = 900001DF (System mode, ARM FIQ dis. IRQ dis.)
    Current:
    R0 =00000000, R1 =FFFFFFFF, R2 =4C00E07F, R3 =F8007000
    R4 =FFFFFF00, R5 =FFFFFF04, R6 =00000018, R7 =F8000004
    R8 =00000008, R9 =00000008, R10=0000767B, R11=E3E0F0D3, R12=F8000244
    R13=EA000049, R14=00000000
    USR: R8 =0000767B, R9 =E3E0F0D3, R10=F8000244, R11=EA000049, R12=00000000
    R13=E5801000, R14=00000000
    FIQ: R8 =00000000, R9 =00000000, R10=00000000, R11=00000000, R12=00000000
    R13=00000000, R14=00000000, SPSR=600F0051
    IRQ: R13=00000000, R14=00000000, SPSR=600F0052
    SVC: R13=00000000, R14=00000048, SPSR=600F0053
    ABT: R13=00000000, R14=00000000, SPSR=600F0057
    UND: R13=00000000, R14=00000000, SPSR=600F005B
    J-Link>s
    00000000: 01 00 80 E2 ADD R0, R0, #0x01
    J-Link>s
    00000004: FD FF FF EA B #-0x0C ; 0x00000000
    J-Link>s
    00000000: 01 00 80 E2 ADD R0, R0, #0x01
    J-Link>s
    00000004: FD FF FF EA B #-0x0C ; 0x00000000
    J-Link>s
    00000000: 01 00 80 E2 ADD R0, R0, #0x01
    J-Link>regs
    PC: (R15) = 00000004, CPSR = 900001DF (System mode, ARM FIQ dis. IRQ dis.)
    Current:
    R0 =00000003, R1 =FFFFFFFF, R2 =4C00E07F, R3 =F8007000
    R4 =FFFFFF00, R5 =FFFFFF04, R6 =00000018, R7 =F8000004
    R8 =0000000C, R9 =0000000C, R10=0000767B, R11=E3E0F0D3, R12=F8000244
    R13=EA000049, R14=00000000
    USR: R8 =0000767B, R9 =E3E0F0D3, R10=F8000244, R11=EA000049, R12=00000000
    R13=E5801000, R14=00000000
    FIQ: R8 =00000000, R9 =00000000, R10=00000000, R11=00000000, R12=00000000
    R13=00000000, R14=00000000, SPSR=600F0051
    IRQ: R13=00000000, R14=00000000, SPSR=600F0052
    SVC: R13=00000000, R14=00000048, SPSR=600F0053
    ABT: R13=00000000, R14=00000000, SPSR=600F0057
    UND: R13=00000000, R14=00000000, SPSR=600F005B
    J-Link>testwspeed
    Speed test: Writing 8 * 128kb into memory @ address 0x00000000 ........
    128 kByte written in 458ms ! (286.0 KByte/sec)
    J-Link>
  • Hi,


    Also tried adding JFlash initialisation steps equivalent to the initialisation performed by the debugger under Source Codebench but still no luck

    Could you provide us with the initialization steps executed by Codebench?

    I can then compare them with what we do internally for the Zedboard......

    Best regards,
    Niklas
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/

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  • Hi Niklas,
    I've attached a JLink log from when I'm starting a debug session from Codebench.
    I've also attached the JFlash project in which I've added init steps.
    Thanks for your continued attention.
    Regards.
    Files
    • JLink_Log.zip

      (4.35 kB, downloaded 443 times, last: )
    • zc702.jflash

      (19.51 kB, downloaded 605 times, last: )
  • Hi,


    sorry for the delay in response.
    The QSPI flash used on the eval board is a N25Q128A, which should work fine.
    Would it be possible for you to provide us access to the board via a J-Link remote Server (Tunnel mode) session?

    10-15 minutes of access time should be enough.

    Best regards,
    Niklas
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/

    Or you can contact us via e-mail.
  • Hi,

    an alternative to setting it up via the company network would be to connect J-Link to a a laptop which is not connected to the company network,
    but instead connected directly or via a mobile phone to a 3G or LTE Network.
    Unfortunately, a teamviewer session does not help, since I need to work with a debug version of our software, which I cannot run on your computer.

    Best regards,
    Niklas
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/

    Or you can contact us via e-mail.
  • Hi,


    thanks for providing access to the board.
    You can close the tunnel session.

    We do not get a valid ID (communication error) from the QSPI flash, although it works on the Zedboard which features the same MCU and connects the QSPI flash to the same pins.
    We assume that the board is unaltered and that Xilinx does not ship $900 boards w/o QA.

    Therefore, I assume it is more generic issue on our side which occurs on this board.
    I requested the eval board from our management. Unfortunately, this might take a while...

    In order to speed things up, would it be possible for you to provide us temporally with the evaluation board?

    Best regards,
    Niklas
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/

    Or you can contact us via e-mail.