Hello,
I've been using IAR EWARM and J-Link Plus to program a Microsemi PSoC chip (A2F500M3G-FGG256) for a few years and have recently run into a problem on one of my boards. I attempted to upload some new code to the CPU and ran into an error: "The floash loader program reported an error."
The IAR-EWARM debug log outputs the following:
Mon Aug 07, 2017 13:31:16: JLINK command: ProjectFile = C:\###REDACTED###.jlink, return = 0
Mon Aug 07, 2017 13:31:16: Device "A2F500M3G" selected.
Mon Aug 07, 2017 13:31:16: DLL version: V6.18
Mon Aug 07, 2017 13:31:16: Firmware: J-Link V9 compiled Jul 24 2017 17:37:57
Mon Aug 07, 2017 13:31:16: Selecting SWD as current target interface.
Mon Aug 07, 2017 13:31:16: JTAG speed is initially set to: 1000 kHz
Mon Aug 07, 2017 13:31:16: Found SW-DP with ID 0x1BA01477
Mon Aug 07, 2017 13:31:16: Scanning AP map to find all available APs
Mon Aug 07, 2017 13:31:16: AP[1]: Stopped AP scan as end of AP map has been reached
Mon Aug 07, 2017 13:31:16: AP[0]: AHB-AP (IDR: 0x14770011)
Mon Aug 07, 2017 13:31:16: Iterating through AP map to find AHB-AP to use
Mon Aug 07, 2017 13:31:16: AP[0]: Core found
Mon Aug 07, 2017 13:31:16: AP[0]: AHB-AP ROM base: 0xE00FF000
Mon Aug 07, 2017 13:31:16: CPUID register: 0x411FC231. Implementer code: 0x41 (ARM)
Mon Aug 07, 2017 13:31:16: Found Cortex-M3 r1p1, Little endian.
Mon Aug 07, 2017 13:31:16: FPUnit: 6 code (BP) slots and 2 literal slots
Mon Aug 07, 2017 13:31:16: CoreSight components:
Mon Aug 07, 2017 13:31:16: ROMTbl[0] @ E00FF000
Mon Aug 07, 2017 13:31:16: ROMTbl[0][0]: E000E000, CID: B105E00D, PID: 001BB000 SCS
Mon Aug 07, 2017 13:31:16: ROMTbl[0][1]: E0001000, CID: B105E00D, PID: 001BB002 DWT
Mon Aug 07, 2017 13:31:16: ROMTbl[0][2]: E0002000, CID: B105E00D, PID: 000BB003 FPB
Mon Aug 07, 2017 13:31:16: ROMTbl[0][3]: E0000000, CID: B105E00D, PID: 001BB001 ITM
Mon Aug 07, 2017 13:31:16: ROMTbl[0][4]: E0040000, CID: B105900D, PID: 001BB923 TPIU-Lite
Mon Aug 07, 2017 13:31:16: Reset: Halt core after reset via DEMCR.VC_CORERESET.
Mon Aug 07, 2017 13:31:16: Reset: Reset device via AIRCR.VECTRESET.
Mon Aug 07, 2017 13:31:16: Hardware reset with strategy 1 was performed
Mon Aug 07, 2017 13:31:16: Initial reset was performed
Mon Aug 07, 2017 13:31:16: 1224 bytes downloaded (25.99 Kbytes/sec)
Mon Aug 07, 2017 13:31:16: Loaded debugee: C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.0\arm\config\flashloader\Microsemi\FlashA2FxxxM3F.out
Mon Aug 07, 2017 13:31:16: Target reset
Mon Aug 07, 2017 13:31:16: The flash loader program reported an error.
I also noticed that the MSS_RESET_N line is pulsing low for about 7 ms every 250 ms. The PSoC is configured to keep the MSS_RESET_N line held low for 250 ms during initial power-on which makes me think the chip is going through its power-on reset routine over and over.
If I disable the flash loader in my Project Settings -> Debugger -> Download tab I am able to attach the debugger to the CPU. The code immediately jumps to the hardfault in this case. One thing I noticed here is that while I am in this mode, the FPGA fabric portion of the PSoC operates normally. I can confirm this via a blinking test LED which is driven by the FPGA fabric's clock and reset lines. Once I disconnect from the chip, the FPGA goes back into a hung state.
Please excuse any ill assumptions I've made in my problem description. I'm usually not this deep in the weeds with this device so I may be short in my understanding. If there's anything else I can add to aid in describing the problem more accurately, just let me know and I'll be more than happy to provide that information.
Thanks for your help
I've been using IAR EWARM and J-Link Plus to program a Microsemi PSoC chip (A2F500M3G-FGG256) for a few years and have recently run into a problem on one of my boards. I attempted to upload some new code to the CPU and ran into an error: "The floash loader program reported an error."
The IAR-EWARM debug log outputs the following:
Mon Aug 07, 2017 13:31:16: JLINK command: ProjectFile = C:\###REDACTED###.jlink, return = 0
Mon Aug 07, 2017 13:31:16: Device "A2F500M3G" selected.
Mon Aug 07, 2017 13:31:16: DLL version: V6.18
Mon Aug 07, 2017 13:31:16: Firmware: J-Link V9 compiled Jul 24 2017 17:37:57
Mon Aug 07, 2017 13:31:16: Selecting SWD as current target interface.
Mon Aug 07, 2017 13:31:16: JTAG speed is initially set to: 1000 kHz
Mon Aug 07, 2017 13:31:16: Found SW-DP with ID 0x1BA01477
Mon Aug 07, 2017 13:31:16: Scanning AP map to find all available APs
Mon Aug 07, 2017 13:31:16: AP[1]: Stopped AP scan as end of AP map has been reached
Mon Aug 07, 2017 13:31:16: AP[0]: AHB-AP (IDR: 0x14770011)
Mon Aug 07, 2017 13:31:16: Iterating through AP map to find AHB-AP to use
Mon Aug 07, 2017 13:31:16: AP[0]: Core found
Mon Aug 07, 2017 13:31:16: AP[0]: AHB-AP ROM base: 0xE00FF000
Mon Aug 07, 2017 13:31:16: CPUID register: 0x411FC231. Implementer code: 0x41 (ARM)
Mon Aug 07, 2017 13:31:16: Found Cortex-M3 r1p1, Little endian.
Mon Aug 07, 2017 13:31:16: FPUnit: 6 code (BP) slots and 2 literal slots
Mon Aug 07, 2017 13:31:16: CoreSight components:
Mon Aug 07, 2017 13:31:16: ROMTbl[0] @ E00FF000
Mon Aug 07, 2017 13:31:16: ROMTbl[0][0]: E000E000, CID: B105E00D, PID: 001BB000 SCS
Mon Aug 07, 2017 13:31:16: ROMTbl[0][1]: E0001000, CID: B105E00D, PID: 001BB002 DWT
Mon Aug 07, 2017 13:31:16: ROMTbl[0][2]: E0002000, CID: B105E00D, PID: 000BB003 FPB
Mon Aug 07, 2017 13:31:16: ROMTbl[0][3]: E0000000, CID: B105E00D, PID: 001BB001 ITM
Mon Aug 07, 2017 13:31:16: ROMTbl[0][4]: E0040000, CID: B105900D, PID: 001BB923 TPIU-Lite
Mon Aug 07, 2017 13:31:16: Reset: Halt core after reset via DEMCR.VC_CORERESET.
Mon Aug 07, 2017 13:31:16: Reset: Reset device via AIRCR.VECTRESET.
Mon Aug 07, 2017 13:31:16: Hardware reset with strategy 1 was performed
Mon Aug 07, 2017 13:31:16: Initial reset was performed
Mon Aug 07, 2017 13:31:16: 1224 bytes downloaded (25.99 Kbytes/sec)
Mon Aug 07, 2017 13:31:16: Loaded debugee: C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.0\arm\config\flashloader\Microsemi\FlashA2FxxxM3F.out
Mon Aug 07, 2017 13:31:16: Target reset
Mon Aug 07, 2017 13:31:16: The flash loader program reported an error.
I also noticed that the MSS_RESET_N line is pulsing low for about 7 ms every 250 ms. The PSoC is configured to keep the MSS_RESET_N line held low for 250 ms during initial power-on which makes me think the chip is going through its power-on reset routine over and over.
If I disable the flash loader in my Project Settings -> Debugger -> Download tab I am able to attach the debugger to the CPU. The code immediately jumps to the hardfault in this case. One thing I noticed here is that while I am in this mode, the FPGA fabric portion of the PSoC operates normally. I can confirm this via a blinking test LED which is driven by the FPGA fabric's clock and reset lines. Once I disconnect from the chip, the FPGA goes back into a hung state.
Please excuse any ill assumptions I've made in my problem description. I'm usually not this deep in the weeds with this device so I may be short in my understanding. If there's anything else I can add to aid in describing the problem more accurately, just let me know and I'll be more than happy to provide that information.
Thanks for your help
The post was edited 2 times, last by L3EDD ().