DAP error while reading AHB-AP IDR

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  • DAP error while reading AHB-AP IDR

    Hello,

    I am trying to debug some problems I am getting with recent versions of J-Link firmware. I use IAR and a J-Link Ultra+ to develop with a Silicon Labs EFR32 Mighty Gecko. I recently upgraded to the latest version of IAR, which upgraded the J-Link firmware and tools, and ever since then i get the error, "DAP error while reading AHB-AP IDR," after pausing, resetting, and running my program on my device. I would normally chalk this up to be an IAR error, but if I revert back to the older version of IAR that worked before I get the same problem. I've updated to the latest J-Link firmware from your site, 6.14f, I still get the same problem. I've tried to replicate the problem in J-Link commander, after connecting to the device I do go, hault, reset, go over and over, but I do not see the problem. I can replicate the problem with J-Flash if I flash the program, click "Start Application", click "Connect", click "Start Application" again, however if I try the same with an application that was compiled with the same IAR version but older J-Link I cannot replicate the problem.

    Any information or further debugging steps would be greatly appreciated.

    Thank You.

  • Hi,

    thanks for your inquiry.

    Could you please provide us with two J-Link logfiles, one of a working and one of a non-working session?

    Log output can be enabled like as follows:
    • Open a connection to J-Link, e.g start J-Link Commander
    • In J-Link Control Panel: (Click the J-Link symbol located in the notification / tray area in order to open J-Link Control panel)
    • Open the tab "Settings"
    • Next to the field "Log file" check "Override" and click "..." in order to choose a log file path.

    This is also described in UM8001 Chapter 5 "Working with J-Link and J-Trace", Section 5.7 "J-Link control panel" .

    Best regards,
    Niklas
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/
    Or you can contact us via e-mail.

  • Here are the log files you requested, j-link-not-working.log (new firmware reproduced with J-Flash), j-link-working.log (old firmware doing the same thing with J-Flash).

    I've tried a few more things since I posted originally:

    Upgraded to beta, 6.15c, this yields the same results as with 6.14f.
    Downgraded the dlls to 6.10n, J-Link firmware still from 6.15c, this fixes the problem.

    Thanks.
    Files

    • j-link.log.zip

      (4.63 kB, downloaded 566 times, last: )

  • Hi,


    sorry, too many things an the ToDo-list...
    I will reserve a time slot for reproduction at the beginning of next week.



    Best regards,
    Niklas
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/
    Or you can contact us via e-mail.

  • I got similar problem, is it J-link issue ?


    "Wed Jun 21, 2017 12:41:08: IAR Embedded Workbench 8.11.2 (C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\bin\armproc.dll)
    Wed Jun 21, 2017 12:41:08: Loaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\config\flashloader\SiliconLaboratories\FlashGECKOP2.mac
    Wed Jun 21, 2017 12:41:08: Device "EFR32MG1BXXXF256" selected.
    Wed Jun 21, 2017 12:41:08: JLINK command: ProjectFile = D:\Projects\client\settings\app_CSL002-Debug.jlink, return = 0
    Wed Jun 21, 2017 12:41:08: Device "EFR32MG1BXXXF256" selected.
    Wed Jun 21, 2017 12:41:08: Selecting SWD as current target interface.
    Wed Jun 21, 2017 12:41:08: JTAG speed is initially set to: 100 kHz
    Wed Jun 21, 2017 12:41:08: Found SW-DP with ID 0x2BA01477
    Wed Jun 21, 2017 12:41:09: Found SW-DP with ID 0x2BA01477
    Wed Jun 21, 2017 12:41:09: No AP preselected. Assuming that AP[0] is the AHB-AP
    Wed Jun 21, 2017 12:41:09: AP-IDR: 0x24770011, Type: AHB-AP
    Wed Jun 21, 2017 12:41:09: AHB-AP ROM: 0xE00FF000 (Base addr. of first ROM table)
    Wed Jun 21, 2017 12:41:09: Found Cortex-M4 r0p1, Little endian.
    Wed Jun 21, 2017 12:41:09: FPUnit: 6 code (BP) slots and 2 literal slots
    Wed Jun 21, 2017 12:41:09: CoreSight components:
    Wed Jun 21, 2017 12:41:09: ROMTbl[0] @ E00FF000
    Wed Jun 21, 2017 12:41:09: ROMTbl[0][0]: E000E000, CID: B105E00D, PID: 000BB00C SCS
    Wed Jun 21, 2017 12:41:09: ROMTbl[0][1]: E0001000, CID: B105E00D, PID: 003BB002 DWT
    Wed Jun 21, 2017 12:41:09: ROMTbl[0][2]: E0002000, CID: B105E00D, PID: 002BB003 FPB
    Wed Jun 21, 2017 12:41:09: ROMTbl[0][3]: E0000000, CID: B105E00D, PID: 003BB001 ITM
    Wed Jun 21, 2017 12:41:09: ROMTbl[0][4]: E0040000, CID: B105900D, PID: 003BB923 TPIU-Lite
    Wed Jun 21, 2017 12:41:09: Warning: Could not set S_RESET_ST
    Wed Jun 21, 2017 12:41:09: Warning: CPU did not halt after reset.
    Wed Jun 21, 2017 12:41:09: Warning: CPU could not be halted
    Wed Jun 21, 2017 12:41:09: Core did not halt after reset, trying to disable WDT.
    Wed Jun 21, 2017 12:41:10: Warning: CPU did not halt after reset.
    Wed Jun 21, 2017 12:41:10: Warning: CPU could not be halted
    Wed Jun 21, 2017 12:41:10: Warning: Could not set S_RESET_ST
    Wed Jun 21, 2017 12:41:10: Found SW-DP with ID 0x2BA01477
    Wed Jun 21, 2017 12:41:10: Using pre-configured AP[0] as AHB-AP to communicate with core
    Wed Jun 21, 2017 12:41:10: Could not power-up system power domain.
    Wed Jun 21, 2017 12:41:11: SYSRESETREQ has confused core. Trying to reconnect and use VECTRESET.
    Wed Jun 21, 2017 12:41:11: Found SW-DP with ID 0x2BA01477
    Wed Jun 21, 2017 12:41:11: Using pre-configured AP[0] as AHB-AP to communicate with core
    Wed Jun 21, 2017 12:41:11: AP-IDR: 0x24770011, Type: AHB-AP
    Wed Jun 21, 2017 12:41:11: AHB-AP ROM: 0xE00FF000 (Base addr. of first ROM table)
    Wed Jun 21, 2017 12:41:11: Found Cortex-M4 r0p1, Little endian.
    Wed Jun 21, 2017 12:41:11: Warning: Failed to reset CPU. VECTRESET has confused core.
    Wed Jun 21, 2017 12:41:11: Warning: CPU did not halt after reset.
    Wed Jun 21, 2017 12:41:11: Warning: CPU could not be halted
    Wed Jun 21, 2017 12:41:11: Core did not halt after reset, trying to disable WDT.
    Wed Jun 21, 2017 12:41:11: Warning: CPU did not halt after reset.
    Wed Jun 21, 2017 12:41:11: Warning: CPU could not be halted Wed Jun 21, 2017 12:41:12: Warning: Could not set S_RESET_ST "

  • Hi,


    I just gave it a try in J-Link Commander and unfortunately could not reproduce any issue.

    Could you please give J-Link Commander a try?
    J-Link commander is part of the J-Link software package, which is available free of charge here .

    • Start J-Link Commander (jlink.exe)
    • Type "connect" in order to start a debug session
    • Type in the target device name if asked (Or type "?" for a target selection Dialog)
    • Choose the correct target interface (JTAG/SWD/etc..)
    • Use a valid speed (Default: 4000kHz, try 100-500 if default does not work)
    • [JTAG only]JTAG conf can be default(most of the times)
    • You should now be successfully connected.
    If anything fails, could you please post a screenshot of the complete session?

    Could you also provide the following information:
    Do you use an eval board or custom hardware?
    Did this setup work in the past?

    Best regards,
    Niklas
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/
    Or you can contact us via e-mail.

  • Here is my error log, appears in irregular intervals, tested with various speed, start from 35kHz.

    "SEGGER J-Link Commander V6.16c (Compiled Jun 16 2017 18:15:26)
    DLL version V6.16c, compiled Jun 16 2017 18:14:49

    Connecting to J-Link via USB...O.K.
    Firmware: Silicon Labs J-Link Pro OB compiled Mar 9 2017 14:47:50
    Hardware version: V4.00
    S/N: 440055730
    IP-Addr: DHCP (no addr. received yet)
    VTref = 3.323V


    Type "connect" to establish a target connection, '?' for help
    J-Link>connect
    Please specify device / core. : EFR32MG1BXXXF256
    Type '?' for selection dialog
    Device>
    Please specify target interface:
    J) JTAG (Default)
    S) SWD
    TIF>s
    Specify target interface speed [kHz]. : 4000 kHz
    Speed>
    Device "EFR32MG1BXXXF256" selected.


    Connecting to target via SWD
    Found SW-DP with ID 0x2BA01477
    Found SW-DP with ID 0x2BA01477
    Scanning APs, stopping at first AHB-AP found.
    Found SW-DP with ID 0x2BA01477
    Found SW-DP with ID 0x2BA01477
    Scanning APs, stopping at first AHB-AP found.
    AP[0] IDR: 0x24770011 (AHB-AP)
    AHB-AP ROM: 0xE00FF000 (Base addr. of first ROM table)
    CPUID reg: 0x410FC241. Implementer code: 0x41 (ARM)
    Found Cortex-M4 r0p1, Little endian.
    FPUnit: 6 code (BP) slots and 2 literal slots
    CoreSight components:
    ROMTbl[0] @ E00FF000
    ROMTbl[0][0]: E000E000, CID: B105E00D, PID: 000BB00C SCS
    ROMTbl[0][1]: E0001000, CID: B105E00D, PID: 003BB002 DWT
    ROMTbl[0][2]: E0002000, CID: B105E00D, PID: 002BB003 FPB
    ROMTbl[0][3]: E0000000, CID: B105E00D, PID: 003BB001 ITM
    ROMTbl[0][4]: E0040000, CID: B105900D, PID: 003BB923 TPIU-Lite

    ****** Error: Connect: Communication error when trying to read IDR of AP[0].
    J-Link>"

  • Hi,

    After the last update 6.16f it is impossible to unsecure the EZR32LG330F256.

    This issue is fixed in version 6.16j and later of the J-Link software & documentation pack.

    Here is my error log, appears in irregular intervals, tested with various speed, start from 35kHz.

    Does this error also occur when using v6.16j?
    If this issue does not occur, does it work for you, or are you experiencing other issues?


    Best regards,
    Niklas
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/
    Or you can contact us via e-mail.

  • I have tested it today, in IAR debugger I often got error: Execution failure in flash loader
    I have checked it in jlink console, works correctly.
    Is there IAR or J-Link issue ?

    Here are my logs:

    "Thu Aug 03, 2017 13:53:38: IAR Embedded Workbench 8.11.2 (C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\bin\armproc.dll)
    Thu Aug 03, 2017 13:53:38: Loaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\config\flashloader\SiliconLaboratories\FlashGECKOP2.mac
    Thu Aug 03, 2017 13:53:38: Device "EFR32MG1PXXXF256" selected.
    Thu Aug 03, 2017 13:53:38: JLINK command: ProjectFile = D:\Projekty\thread\sources\connector\settings\connector_EFR32MG1P-Debug.jlink, return = 0
    Thu Aug 03, 2017 13:53:38: Device "EFR32MG1PXXXF256" selected.
    Thu Aug 03, 2017 13:53:38: JTAG speed is initially set to: 32 kHz
    Thu Aug 03, 2017 13:53:38: TotalIRLen = ?, IRPrint = 0x..FFFFFFFFFFFFFFFFFFFFFFF1
    Thu Aug 03, 2017 13:53:38: Secured EFR32 device detected. This could cause problems during flash download.
    Thu Aug 03, 2017 13:53:38: Note: Unsecuring will trigger a mass erase of the internal flash.
    Thu Aug 03, 2017 13:53:38: Executing default behavior previously saved in the registry.
    Thu Aug 03, 2017 13:53:38: Device will be unsecured now.
    Thu Aug 03, 2017 13:53:38: Found SW-DP with ID 0x2BA01477
    Thu Aug 03, 2017 13:53:38: Scanning APs, stopping at first AHB-AP found.
    Thu Aug 03, 2017 13:53:38: AP[0] IDR: 0x24770011 (AHB-AP)
    Thu Aug 03, 2017 13:53:38: AHB-AP ROM: 0xE00FF000 (Base addr. of first ROM table)
    Thu Aug 03, 2017 13:53:38: CPUID reg: 0x410FC241. Implementer code: 0x41 (ARM)
    Thu Aug 03, 2017 13:53:38: Found Cortex-M4 r0p1, Little endian.
    Thu Aug 03, 2017 13:53:38: FPUnit: 6 code (BP) slots and 2 literal slots
    Thu Aug 03, 2017 13:53:38: CoreSight components:
    Thu Aug 03, 2017 13:53:38: ROMTbl[0] @ E00FF000
    Thu Aug 03, 2017 13:53:38: ROMTbl[0][0]: E000E000, CID: B105E00D, PID: 000BB00C SCS
    Thu Aug 03, 2017 13:53:38: ROMTbl[0][1]: E0001000, CID: B105E00D, PID: 003BB002 DWT
    Thu Aug 03, 2017 13:53:38: ROMTbl[0][2]: E0002000, CID: B105E00D, PID: 002BB003 FPB
    Thu Aug 03, 2017 13:53:38: ROMTbl[0][3]: E0000000, CID: B105E00D, PID: 003BB001 ITM
    Thu Aug 03, 2017 13:53:38: ROMTbl[0][4]: E0040000, CID: B105900D, PID: 003BB923 TPIU-Lite
    Thu Aug 03, 2017 13:53:38: Setting AIRCR.SYSRESETREQ
    Thu Aug 03, 2017 13:53:38: Hardware reset with strategy 0 was performed
    Thu Aug 03, 2017 13:53:38: Initial reset was performed
    Thu Aug 03, 2017 13:53:38: Found 1 JTAG device, Total IRLen = 4:
    Thu Aug 03, 2017 13:53:38: Setting up GECKOP2 flash
    Thu Aug 03, 2017 13:53:38: 1024 bytes downloaded and verified (16.13 Kbytes/sec)
    Thu Aug 03, 2017 13:53:38: Loaded debugee: C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\config\flashloader\SiliconLaboratories\FlashGECKOP2.out
    Thu Aug 03, 2017 13:53:38: Target reset
    Thu Aug 03, 2017 13:53:38: Unloaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\config\flashloader\SiliconLaboratories\FlashGECKOP2.mac
    Thu Aug 03, 2017 13:53:38: Execution failure in flash loader. Thu Aug 03, 2017 13:53:50: IAR Embedded Workbench 8.11.2 (C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\bin\armproc.dll) "


    "SEGGER J-Link Commander V6.16j (Compiled Jul 24 2017 18:42:58)
    DLL version V6.16j, compiled Jul 24 2017 18:42:23

    Connecting to J-Link via USB...O.K.
    Firmware: Silicon Labs J-Link Pro OB compiled Mar 9 2017 14:47:50
    Hardware version: V4.00
    S/N: 440048406
    IP-Addr: DHCP (no addr. received yet)
    VTref = 3.329V


    Type "connect" to establish a target connection, '?' for help
    J-Link>connect
    Please specify device / core. : EFR32MG1PXXXF256
    Type '?' for selection dialog
    Device>
    Please specify target interface:
    J) JTAG (Default)
    S) SWD
    TIF>S
    Specify target interface speed [kHz]. : 4000 kHz
    Speed>
    Device "EFR32MG1PXXXF256" selected.


    Connecting to target via SWD
    Found SW-DP with ID 0x2BA01477
    Found SW-DP with ID 0x2BA01477
    Scanning APs, stopping at first AHB-AP found.
    AP[0] IDR: 0x24770011 (AHB-AP)
    AHB-AP ROM: 0xE00FF000 (Base addr. of first ROM table)
    CPUID reg: 0x410FC241. Implementer code: 0x41 (ARM)
    Found Cortex-M4 r0p1, Little endian.
    FPUnit: 6 code (BP) slots and 2 literal slots
    CoreSight components:
    ROMTbl[0] @ E00FF000
    ROMTbl[0][0]: E000E000, CID: B105E00D, PID: 000BB00C SCS
    ROMTbl[0][1]: E0001000, CID: B105E00D, PID: 003BB002 DWT
    ROMTbl[0][2]: E0002000, CID: B105E00D, PID: 002BB003 FPB
    ROMTbl[0][3]: E0000000, CID: B105E00D, PID: 003BB001 ITM
    ROMTbl[0][4]: E0040000, CID: B105900D, PID: 003BB923 TPIU-Lite
    Cortex-M4 identified.
    J-Link>"

  • Hi,

    Execution failure in flash loader

    This is an error message by IAR.


    Could you please go to the project settings and make sure that the following box is unchecked?:



    Best regards,
    Niklas
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/
    Or you can contact us via e-mail.

  • I have unchecked this option, debugger starts without error every time, but has often problem with stability during debug, I got disconnect or retry window.
    I come back this function, and put ticket do IAR support.

  • Hi,


    I have unchecked this option, debugger starts without error every time,

    Sounds good.

    but has often problem with stability during debug, I got disconnect or retry window.

    Do you use low power-modes in your application?
    Some low power modes interfere or even disable the debug interface, which can cause J-Link to loose the connection.


    Best regards,
    Niklas
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/
    Or you can contact us via e-mail.

  • Hi Niklas

    No, I don't have low power mode.
    It is better when chip is empty.
    In external tool Simplicity Commander I click "Unlock debug access" or "Erase chip" - I don't have debugger breakdown.

  • Hi,


    sorry for the delay in response.
    Does this issue also occur with a simple application, like a loop which increments a counter?

    I got disconnect or retry window

    Could you please provide us with a screenshot of the error message?
    Could you please also provide us with the output of IAR of a session where the error ocurred?


    Best regards,
    Niklas
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/
    Or you can contact us via e-mail.

  • Hi Niklas

    I will check on simple project.

    Today I have another error in IAR.
    Here is my screen: [img]https://ibb.co/etcoKv[/img] ibb.co/etcoKv




    If this error occurs, choose:
    - YES - I can't run the IAR debugger, despite many attempts, then I run jlink.exe connect to MCU without any problems, close jlink.exe, come back to IAR and debugger can start correctly.
    - NO - debugger starts, but after 1-2s I got message "Failed to get CPU status after 4 retries Retry?"






    I have checked on simple project, main with i++ counter, I don't have problems with stability.
    I have stability issue and error "Failed to get CPU status after 4 retries Retry?" when my code are using other MCU peryferials: gpio, uart and radio.

    The post was edited 1 time, last by tj7 ().

  • Hi,

    when my code are using other MCU peryferials: gpio, uart and radio.

    Is it possible for you to isolate the code which is causing this issue?


    Best regards,
    Niklas
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/
    Or you can contact us via e-mail.