[ANSWERED] Live watch on TMS570

iguffick · Sep 15th 2016, 3:51pm

I'm trying to debug with IAR EWARM, a Jlink Ultra+ and a TMS570LS20216 / TMS570LS3137 (on two separate boards).

When I debug with other processors (e.g STM32) I can see values changing in the 'Live Watch' window whilst the core is running.
With the TMS570 processors I have to halt the core for these values to update.

Is this a known limitation with the TMS570 processors, a feature that isn't implemented on these processors or a bug in JLink or IAR EWARM?

Is anyone else using the TMS570 series with Live Watch working?

BR,
Ian.

SEGGER - Niklas · Sep 15th 2016, 4:13pm

Hi Ian,

While IAR EWARM is not a SEGGER product, I assume that IAR is using the "background memory access" feature of Cortex-M cores that allows to read / write the target's RAM while the target device is running.
On Cortex-A and Cortex-R cores this feature is optional, but not mandatory.
Therefore, you need to check
a) If TMS570LS20216 / TMS570LS3137 support background memory access (Both Cortex-R4F cores)
b) If IAR supports Live Watch on Cortex-A and Cortex-R cores which support background memory access.

Best regards,
Niklas

iguffick · Sep 15th 2016, 4:31pm

Hi Niklas,

Thanks for the reply.

I had already asked IAR directly if this feature should work in EWARM and had this response:

"This J-link behavior is not controlled by us. Refer to Segger support.From the TMS570LS21x reference manual's Architecture Block Diagram it
appears that the DAP is connected to the memory bus independently from the
CPU, so it's quite possible that reading while running is possible to do on
this device. So, to get it working on a J-Link Segger needs to implement it."

They clearly think that it's the way it is implemented in the debug tool (JLink) that determines if this works or not.

Texas Instruments own tool CCS and XDS debugger do allow and work with live watch, so I presume it is possible on this processor.
I remember reading a thread some time ago about the TMS570 being different to other Cortex devices, in that it does this access through the DAP, not the usual CPU access. Although I can't find that thread to get the exact detail!
This might be to ensure both cores remain in lockstep.

Any thoughts?

BR,
Ian.

iguffick · Sep 27th 2016, 11:03am

Hi,

I've done some further digging and found this PDF about JTAG on the device.

ti.com/lit/an/spna230/spna230.pdf

Relevent section is:
Page 13, section 2.3.2 Accessing the System Memory Mapped Resources

"This is a fast way to access the system memories without halting
the CPU".

So it seems that live watch with the processor running can be achieved on this processor.
But my question, is this handled by Segger in JLink or is this part of what IAR EWARM would do?

Regards,
Ian.

SEGGER - Niklas · Sep 27th 2016, 11:37am

Hi Ian,

sorry for the delay in response.
I will try to find a time window later today to test this with SEGGER Embedded Studio / IAR EWARM + J-Link and come back to you with the results.

Best regards,
Niklas

SEGGER - Niklas · Sep 28th 2016, 9:56am

Hi Ian,

Currently, background memory access for Cortex-A/R(if AHB is specified via "exec CORESIGHT_SetIndexAHBAPToUse <value>") devices is only possible with RTT. Support for general memory accesses is already on our internal ToDo, but whithout a planned release date yet.
When support is implemented, it will be only available in Ozone and SEGGER Embedded Studio.
IAR will most likely have to change how they read memory of the target device when using J-Link.

Best regards,
Niklas

iguffick · Sep 28th 2016, 10:21am

Hi Niklas,

Ok, thanks for the update.
I'll have a look at getting RTT to work.

Regards,
Ian.

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