[SOLVED] JLink and STM32F411CE problem

This site uses cookies. By continuing to browse this site, you are agreeing to our Cookie Policy.

  • [SOLVED] JLink and STM32F411CE problem

    Hi all,

    I've a simple board to test STM32F411CE and a JLink Edu to program it through the SWD. I can connect to the host, but when it comes to programming the flash (I'm using Eclipse and the GNU plugin for ARM) I got errors like "Failed to prepare for programming", "Failed to execute RAMCode for RAM check", etc. I thought this could be the same error about WWDG-SW bit unset found here:

    [SOLVED] STM32F746 Failed to execute RAMCode for RAM check! after upgrade to jlink 5.02e

    But here are the option bytes and they seem to be correct:

    J-Link>connect
    Device "STM32F411CE" selected.

    J-Link>mem32 40023c0c 1

    ****** Error: Failed to prepare for programming.
    RAM check failed @ addr 0x200007B0.
    RAM check failed while testing 0x0450 bytes @ addr 0x200006F4.
    40023C0C = 00000000
    Found SWD-DP with ID 0x2BA01477
    Found SWD-DP with ID 0x2BA01477
    Found Cortex-M4 r0p1, Little endian.
    FPUnit: 6 code (BP) slots and 2 literal slots
    CoreSight components:
    ROMTbl 0 @ E00FF000
    ROMTbl 0 [0]: FFF0F000, CID: B105E00D, PID: 000BB00C SCS
    ROMTbl 0 [1]: FFF02000, CID: B105E00D, PID: 003BB002 DWT
    ROMTbl 0 [2]: FFF03000, CID: B105E00D, PID: 002BB003 FPB
    ROMTbl 0 [3]: FFF01000, CID: B105E00D, PID: 003BB001 ITM
    ROMTbl 0 [4]: FFF41000, CID: B105900D, PID: 000BB9A1 TPIU
    ROMTbl 0 [5]: FFF42000, CID: B105900D, PID: 000BB925 ETM
    Cortex-M4 identified.
    J-Link>mem32 1fffc000 4
    1FFFC000 = 5510AAEF 5510AAEF C0003FFF C0003FFF

    That is, AA (no read protection), E (no reset generated, SW watchdog, WWDG-SW set), F (BOR off).

    I've also read about testing the SWD connection with ST Link:

    [SOLVED] Bricking STM32F4 after failed programming

    Here a test I've done to understand what is going on (this is, resetting flash register Flash status register FLASH_SR and reading the value back again):

    JLinkExe -device STM32F411CE -if SWD -speed 1000
    SEGGER J-Link Commander V5.10u (Compiled Mar 17 2016 19:06:22)
    DLL version V5.10u, compiled Mar 17 2016 19:06:19

    Connecting to J-Link via USB...O.K.
    Firmware: J-Link V9 compiled Mar 15 2016 18:03:32
    Hardware version: V9.30errors
    S/N: 2693047
    License(s): FlashBP, GDB
    OEM: SEGGER-EDU
    VTref = 3.338V


    Type "connect" to establish a target connection, '?' for help
    J-Link>connect
    Device "STM32F411CE" selected.


    Found SWD-DP with ID 0x2BA01477
    Found SWD-DP with ID 0x2BA01477
    Found Cortex-M4 r0p1, Little endian.
    FPUnit: 6 code (BP) slots and 2 literal slots
    CoreSight components:
    ROMTbl 0 @ E00FF000
    ROMTbl 0 [0]: FFF0F000, CID: B105E00D, PID: 000BB00C SCS
    ROMTbl 0 [1]: FFF02000, CID: B105E00D, PID: 003BB002 DWT
    ROMTbl 0 [2]: FFF03000, CID: B105E00D, PID: 002BB003 FPB
    ROMTbl 0 [3]: FFF01000, CID: B105E00D, PID: 003BB001 ITM
    ROMTbl 0 [4]: FFF41000, CID: B105900D, PID: 000BB9A1 TPIU
    ROMTbl 0 [5]: FFF42000, CID: B105900D, PID: 000BB925 ETM
    Cortex-M4 identified.
    J-Link>r
    Reset delay: 0 ms
    Reset type NORMAL: Resets core & peripherals via SYSRESETREQ & VECTRESET bit.
    J-Link>h
    PC = FFFFFFFE, CycleCnt = 00000000
    R0 = 00000000, R1 = 00000000, R2 = 00000000, R3 = 00000000
    R4 = 00000000, R5 = 00000000, R6 = 00000000, R7 = 00000000
    R8 = 00000000, R9 = 00000000, R10= 00000000, R11= 00000000
    R12= 00000000
    SP(R13)= FFFFFFFC, MSP= FFFFFFFC, PSP= 00000000, R14(LR) = FFFFFFFF
    XPSR = 01000000: APSR = nzcvq, EPSR = 01000000, IPSR = 000 (NoException)
    CFBP = 00000000, CONTROL = 00, FAULTMASK = 00, BASEPRI = 00, PRIMASK = 00
    FPU regs: FPU not enabled / not implemented on connected CPU.
    J-Link>mem32 40023c0c 1
    40023C0C = 00000000
    J-Link>mem32 0 1
    00000000 = FFFFFFFF
    J-Link>w1 0 1
    Writing 01 -> 00000000
    J-Link>mem32 0 1
    00000000 = FFFFFFFF
    J-Link>mem32 40023c0c 1J-Link>connect
    Device "STM32F411CE" selected.


    Found SWD-DP with ID 0x2BA01477
    Found SWD-DP with ID 0x2BA01477
    Found Cortex-M4 r0p1, Little endian.
    FPUnit: 6 code (BP) slots and 2 literal slots
    CoreSight components:
    ROMTbl 0 @ E00FF000
    ROMTbl 0 [0]: FFF0F000, CID: B105E00D, PID: 000BB00C SCS
    ROMTbl 0 [1]: FFF02000, CID: B105E00D, PID: 003BB002 DWT
    ROMTbl 0 [2]: FFF03000, CID: B105E00D, PID: 002BB003 FPB
    ROMTbl 0 [3]: FFF01000, CID: B105E00D, PID: 003BB001 ITM
    ROMTbl 0 [4]: FFF41000, CID: B105900D, PID: 000BB9A1 TPIU
    ROMTbl 0 [5]: FFF42000, CID: B105900D, PID: 000BB925 ETM
    Cortex-M4 identified.
    J-Link>mem32 1fffc000 4
    1FFFC000 = 5510AAEF 5510AAEF C0003FFF C0003FFF

    40023C0C = 00000080
    J-Link>w4 40023c0c 80
    Writing 00000080 -> 40023C0C
    J-Link>mem32 40023c0c 1
    40023C0C = 00000000
    J-Link>mem32 0 1
    00000000 = FFFFFFFF
    J-Link>w1 0 1
    Writing 01 -> 00000000
    J-Link>mem32 0 1
    00000000 = FFFFFFFF
    J-Link>mem32 40023c0c 1
    40023C0C = 00000080
    J-Link>w4 40023c0c 80
    Writing 00000080 -> 40023C0C
    J-Link>mem32 40023c0c 1
    40023C0C = 00000000
    J-Link>w4 0 1
    Writing 00000001 -> 00000000
    J-Link>mem32 0 1
    00000000 = 00000001
    J-Link>mem32 40023c0c 1

    ****** Error: Failed to prepare for programming.
    RAM check failed @ addr 0x200007B0.
    RAM check failed while testing 0x0450 bytes @ addr 0x200006F4.
    40023C0C = 00000000
    J-Link>mem32 200007ac 1
    200007AC = 000000B8
    J-Link>mem32 200007b0 1
    200007B0 = 000000BC
    J-Link>mem32 200007b4 1
    200007B4 = 000000C0
    J-Link>mem32 200007b8 1
    200007B8 = 000000C4
    J-Link>

    Can someone help?

    Thanks in advance

    Andrew

  • Hi Andrew,


    I just checked tried to reproduce this issue with an Nucleo STM32F411RE here, but it works fine for me.
    Could you try to create a J-Link Commandfile that reliable reproduces this issue with your setup and post it here?
    Could you also post a J-Link logfile?

    Log output can be enabled like as follows:
    • Open a connection to J-Link, e.g start J-Link Commander
    • In J-Link Control Panel: (Click the J-Link symbol located in the notification / tray area in order to open J-Link Control panel)
    • Open the tab "Settings"
    • Next to the field "Log file" check "Override" and click "..." in order to choose a log file path.

    This is also described in UM8001 Chapter 5 "Working with J-Link and J-Trace", Section 5.7 "J-Link control panel" .

    Best regards,
    Niklas
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/
    Or you can contact us via e-mail.

  • Dear Niklas,

    thanks for the support, I apologize for the very late reply but I didn't have time to verify what was wrong with my board.
    Since you confirmed the correct behaviour of J-Link, I've investigated the issue at PCB level and found that the cap for the internal regulator was not properly soldered.
    I can program the MCU, problem solved. :thumbsup:

    Andrew

    The post was edited 1 time, last by student47 ().

  • Hi Andrew,

    Thanks for confirmation and good to hear that you are up and running now!

    Best regards,
    Niklas
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/
    Or you can contact us via e-mail.