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IngeTorsvik

Beginner

Date of registration: Mar 18th 2016

Posts: 3

1

Friday, March 18th 2016, 12:08pm

[ABANDONED] JTAG chain - CPU-TAP not found

I have a JTAG-chain consisting of a VF6XX_A5 MCU and a Igloo nano FPGA. I am using J_Link PlUS, and I know that I can not expect to program the FPGA out of the box, but shouldn't I be able to program the MCU, even though there are a FPGA on the chain?


The chain is configured as following:

TDI --> VF6XX_A5 (IRlen 4) --> Igloo nano (IRlen 8) -->
TDO <--------------------------------------------------------


I am using J_link Commander to try to connect to the MCU.
The setting I am using is
Device: VF6XX_A5,
TIF: JTAG,
JTAGConf: -1,-1 (I have tried 0,0 which should be the correct according my setup)
Speed 4000 KHz

But the respons i get is:
Device "VF6XX_A5" selected.


TotalIRLen = 12, IRPrint = 0x019D
TotalIRLen = 12, IRPrint = 0x019D
TotalIRLen = 12, IRPrint = 0x019D
TotalIRLen = 12, IRPrint = 0x019D

****** Error: CPU-TAP not found in JTAG chain

TotalIRLen = 12, IRPrint = 0x019D
TotalIRLen = 12, IRPrint = 0x019D
TotalIRLen = 12, IRPrint = 0x019D
TotalIRLen = 12, IRPrint = 0x019D

****** Error: CPU-TAP not found in JTAG chain

Can not connect to target.

Can anyone help me? I am out if ideas..

SEGGER - Niklas

Super Moderator

Date of registration: Oct 6th 2014

Posts: 1,691

2

Tuesday, March 22nd 2016, 6:10pm

Hi,

if you do not connect to the target but use the JTAG Commands provided by J-Link Commander like e.g. described in this post,
do you get the excepted response (IDCODE) of the A5? If not, does it work with SEGGER JTAGLoad?


Best regards,
Niklas
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nikhilesh

Beginner

Date of registration: Mar 21st 2016

Posts: 4

3

Thursday, March 24th 2016, 4:38pm

Hi Inge Torsvik,
Please verify if the boundary scan mode is enable on your MCU. To communicate to JTAG you have to select JTAG & CJTAG mode.

Supported modes by VF6XX_A5 MCU:
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug


Regards,
Nikhilesh

IngeTorsvik

Beginner

Date of registration: Mar 18th 2016

Posts: 3

4

Tuesday, January 31st 2017, 8:33am

Hi Nikhilesh and Niklas

Sorry my very delayed respons on this. We decided at that it wasn't necessary to connect to the devices in a chain anymore, and so we didn't need to spend time on this. But now this up as a topic again.

Do you have any ide on how to set the vybrid in boundary scan mode. What I found in the referance manual is this:


JTAG-toJTAG to cJTAG change sequence
• Reset the debug port.
• Set the control level to 2 via the zero-bit scans.
• Execute the Store Format (STFMT) command (00011) to set the scan format register 1149.7 scan format.

But I don't know what zero-bit scan is, or how this can be done. Any ideas?

IngeTorsvik

Beginner

Date of registration: Mar 18th 2016

Posts: 3

5

Tuesday, January 31st 2017, 10:03am

I am able to verify the device id of the Igloo FPGA by using the following svf commands:
!Begin Test Program
ENDIR IDLE; !End IR scans in IDLE
ENDDR IDLE; !End DR scans in IDLE
SDR 32 TDI (0) TDO (1BA541CF); !32-bit DR scan
!End Test Program

And able to read the vybrid id by using these commands in JLINk Commander:
J-Link>wjc 0xe
Command 0xE (IDCODE) successfully written
J-Link>wjd 0,32
returns 0x4BA00477
J-Link>

I have also tested the chain with topjtag (evaluation version), which works fine.

So why doesn't work with Jlink commander?